ASML Q1-18 Results: Multiple EUV Orders, 4 High-NA for R&D in 2021 and HVM in 2024

[Fred Chen]

Your statement is simply not logical. There is no correlation between being confident in EUV and doing 8nm. 8nm is useful in maxing out quadruple patterning feature reduction, it allows earlier introduction with high-volume tools since EUV is supply constrained and thus there is not enough EUV equipment available for a direct jump to 7nm within the same timeframe.

Unless EUV is not available in their desired timeframe, there is actually no logic to introduce 8nm since it adds the extra steps Samsung was trying to avoid by going to EUV. The shrink is also minimal, for all the extra effort. So, as I said, there is no confidence EUV will fit their schedule.

 

[DrizztVD]

The 8nm does not add any of the extra steps that would be required if not using EUV on a hyperscaled node, because 8nm only shrinks far enough to be useful but not beyond what can already be done with DUV. Look at Intel- they tried using hex-patterning because they thought they could just 'make it work' with DUV and hyperscaling. They failed.

 

[Fred Chen]

The 8nm does not add any of the extra steps that would be required if not using EUV on a hyperscaled node, because 8nm only shrinks far enough to be useful but not beyond what can already be done with DUV. Look at Intel- they tried using hex-patterning because they thought they could just 'make it work' with DUV and hyperscaling. They failed.

The VLSI 2018 press kit summary mentions Samsung 8LPP uses LE^4 quadruple patterning to get 15% area reduction over 10LPP (which used triple patterning). LE^4 was considered to be over the tipping point for allowable multipatterning, but maybe it's different now. Not sure how Intel managed to get to hex patterning. Their 14nm metal is dual patterning.

 

[Lodix]

The VLSI 2018 press kit summary mentions Samsung 8LPP uses LE^4 quadruple patterning to get 15% area reduction over 10LPP (which used triple patterning). LE^4 was considered to be over the tipping point for allowable multipatterning, but maybe it's different now. Not sure how Intel managed to get to hex patterning. Their 14nm metal is dual patterning.

Last I saw from Samsung was a 10% area reduction. Can you share the source ?

 

[Fred Chen]

Last I saw from Samsung was a 10% area reduction. Can you share the source ?

http://vlsisymposium.org/wp-content...018-VLSI-tip-sheet-combined-FINAL-4.17.18.pdf

View attachment 21680

 

[Lodix]

http://vlsisymposium.org/wp-content...018-VLSI-tip-sheet-combined-FINAL-4.17.18.pdf

View attachment 21680

Thanks.
It is interesting to see that their PPA targets for 7LPP here are higher than what they claimed recently. Samsung tees up the world’s first commercial EUV chips - Voices@SamsungSemiconductorVoices@SamsungSemiconductor

Maybe in the symposium preview they are comparing 7LPP vs 10LPE and in the Samsung's Blog they are talking about 7LPP vs 10LPP.

With 10nm when talking about its benefits Samsung only compared it to 14LPE to make it look better, so I was under the impression that they were doing the same now with 7nm. And I was a bit underwhelmed about their small 10% performance improvement.

 

[Fred Chen]

Found this surprisingly good update on EUV: The Annual Lithography Issue – EEJournal

 

[user nl]

EUV in Final Push into Fabs

Making progress amid a lot of pressure

Rick Merritt

ANTWERP, Belgium — A 20-year struggle to launch a next-generation lithography tool has entered its final phase as engineers race to unravel a rat’s nest of related issues. Despite complex problems and short deadlines to bring extreme ultraviolet (EUV) steppers into high-volume manufacturing, experts remain upbeat.
The good news is that many shoulders are pushing the wheel ahead. “In the past, one company would take a lead with a new semiconductor technology, but now all the logic guys are jumping in, biting the bullet, and taking the risks,” said An Steegen, executive vice president of technology and systems at Imec.
The research institute in Belgium is a long-standing collaborator with ASML, the developer of EUV in the Netherlands. Together with foundries and suppliers, they now aim to work out the last major kinks in the room-sized systems that will print next-generation chips.

https://www.eetimes.com/document.asp?_mc=RSS_EET_EDT&doc_id=1333326&page_number=1