I recently studied an IMEC paper (with the help of Scotten Jones, I should mention), its citation is as follows:
S. M. Y. Sherzi, B. Chava, P. Debacker, M. G. Bardon, P. Schuddinck, F. Firouzi, P. Raghavan, A Mercha, D. Verkest, and J. Ryckaert, "Architectural strategies in standard-cell design for the 7 nm and beyond technology node", J. Micro/Nanolith. MEMS MOEMS, 15 013507 (Jan-Mar 2016), (c) 2016 SPIE.
The paper presented some key cases of standard cell layouts with minimized SAQP burden, although such burden is still heavy, and also incurred the addition of significant MOL (Middle-Of-Line) processing to help make things easier for the BEOL.
But there was one graph that was particularly interesting, Figure 2, which, aside from being a nice pitch roadmap picture, mentioned an "8nm" node, or more specifically "N8". On this graph I also indicated by colored ellipses 2 actual and 3 extrapolated stopping points:
"10nm": CPP=64 nm, MMP=48 nm (Samsung)
"8nm": CPP=54 nm, MMP=40 nm (Intel/TSMC)
"7nm": CPP=45 nm, MMP=32 nm (extrapolated)
"6nm": CPP=34 nm, MMP=26 nm (extrapolated) (This name came from it being located between N5 and N7 curves)
"5nm": CPP=24 nm, MMP=18 nm (extrapolated)
View attachment 18868
In fact, the paper focused on the CPP=42 nm, MMP=32 nm case, indicated by the star, which is a fair representative of N7 or "7nm". The larger 9-track examples did not impose much SAQP burden as far as block masks were concerned, but the 7.5-track examples made use of a new MOL layer, MINT, which is a harder SAQP layer. "6nm" and "5nm" look unimaginable even with projected EUV assistance, which means two EUV exposures for the tightest pitch metal layers.
But the interesting thing to note now is that the 8nm node point is marked by MMP=40 nm and CPP=54 nm, which is a combination of the recently announced TSMC 7nm and Intel 10nm pitches, respectively. So "8nm" looks like some appropriate average node name for the current status quo.
It will be interesting how the node names progress, if TSMC 5nm and Intel 7nm and Samsung 7nm actually are closer to the "7nm" CPP=42nm, MMP=32 nm point in the graph above.
S. M. Y. Sherzi, B. Chava, P. Debacker, M. G. Bardon, P. Schuddinck, F. Firouzi, P. Raghavan, A Mercha, D. Verkest, and J. Ryckaert, "Architectural strategies in standard-cell design for the 7 nm and beyond technology node", J. Micro/Nanolith. MEMS MOEMS, 15 013507 (Jan-Mar 2016), (c) 2016 SPIE.
The paper presented some key cases of standard cell layouts with minimized SAQP burden, although such burden is still heavy, and also incurred the addition of significant MOL (Middle-Of-Line) processing to help make things easier for the BEOL.
But there was one graph that was particularly interesting, Figure 2, which, aside from being a nice pitch roadmap picture, mentioned an "8nm" node, or more specifically "N8". On this graph I also indicated by colored ellipses 2 actual and 3 extrapolated stopping points:
"10nm": CPP=64 nm, MMP=48 nm (Samsung)
"8nm": CPP=54 nm, MMP=40 nm (Intel/TSMC)
"7nm": CPP=45 nm, MMP=32 nm (extrapolated)
"6nm": CPP=34 nm, MMP=26 nm (extrapolated) (This name came from it being located between N5 and N7 curves)
"5nm": CPP=24 nm, MMP=18 nm (extrapolated)
View attachment 18868
In fact, the paper focused on the CPP=42 nm, MMP=32 nm case, indicated by the star, which is a fair representative of N7 or "7nm". The larger 9-track examples did not impose much SAQP burden as far as block masks were concerned, but the 7.5-track examples made use of a new MOL layer, MINT, which is a harder SAQP layer. "6nm" and "5nm" look unimaginable even with projected EUV assistance, which means two EUV exposures for the tightest pitch metal layers.
But the interesting thing to note now is that the 8nm node point is marked by MMP=40 nm and CPP=54 nm, which is a combination of the recently announced TSMC 7nm and Intel 10nm pitches, respectively. So "8nm" looks like some appropriate average node name for the current status quo.
It will be interesting how the node names progress, if TSMC 5nm and Intel 7nm and Samsung 7nm actually are closer to the "7nm" CPP=42nm, MMP=32 nm point in the graph above.
Last edited: