Question - when ARM creates a new ARM core or ARM IP and then goes to TSMC to fab test versions of it on the latest nodes.. do they also do this at Samsung or not?
Some clarifying points:
1) ARM develops physical IP design in addition to Soft IP (Physical is their std cell libraries and memory IP, which they license out as POP kits for their CPU / GPU soft IP; sometimes also GPIOs, but that is about it). ARM have made POP kits available on Samsung S7LPP and S5LPE from what I've seen announced at previous SFFs, but unclear about anything more recent.
2) ARM very occasionally will develop a POC or development vehicle, that includes physical implementations of their CPU or GPU IP; typically this is done only when there is a new ISA change and they want to seed development community with this device for early software development outside of their own internal migration.
Otherwise, ARM only develops their IP on FPGAs / emulation environments and licenses that soft IP to customers, who are the first to physically implement it, either with Foundry physical IP, or with POP kits. I can think of one instance in the past decade where ARM put an early CPU on N10 in support of a specific customer, but otherwise when you see claims from TSMC or Samsung Foundry about ARM CPU performance, it is the Foundry doing the implementation of that IP (Cortex A72, A53, etc), not ARM. They might use a Foundry PDK to validate that their IP meets specific PPA claims, but that doesn't mean they are going to drop that onto a shuttle.
You would see ARM cores used for PPA claims at events like SNUG / CDNLive / DAC, but again these are typically a customer (Mediatek), the EDA companies, or the Foundries themselves doing the presentation, and maybe ARM is there as a partner on the project. ARM has also done some interesting testchips to test concepts like 3D stacking / core folding (Trishul) but they are using proven CPU or fabric IP for that (keeps the bugs limited to their POC vs the IP), and again it is unclear to me if they took those projects from a converged design (what they share in publications) to actual silicon.
