An interview with Tom Caulfield and a second interview with Ann Kelleher
- Thread starter nghanayem
- Start date
What does everyone think about Intel's 4 nodes in 5 years pitch? Does Intel 4, 3, 20A, and 18A qualify as separate nodes? And when does a node qualify as completed?
How does that compare with what TSMC does? How many nodes will TSMC complete in the same 5 years?
I know we are talking about PR spins and such but I think it is important to set expectations properly. Why should semiconductor insiders operate on different data than outsiders?
How does that compare with what TSMC does? How many nodes will TSMC complete in the same 5 years?
I know we are talking about PR spins and such but I think it is important to set expectations properly. Why should semiconductor insiders operate on different data than outsiders?
tooLongInEDA
Moderator
I think we just need to roll with the "post-truth" nature of modern process labelling and embrace the chaos. The truth will out through the adoption and sales of the varies processes (and associated IP ecosystems) in complete chips (or at least chiplets). Of course, industry outsiders won't get to see the yield numbers and things like ARM core benchmarks used to compare the processes, but that's never really been the case. So the outsider insight lags the insiders by some time constant (likely at least a year).
Why not simply think of these processes as products (like cars) ? Or call them "platforms" if we must. Intel then offers a range of products targetting various markets. TSMC does the same - but serves a wider range of markets, but is not necessarily a super-set of Intel. What you decide to launch is a combination of your business/marketing strategy, technical capability and resources. These likely vary widely across Intel, TSMC and Samsung. And also a little depending on the size and sophistication of the customers served. It (comparing foundry offerings) is too complex to reduce to simple metrics like process feature sizes anyway.
I think Dan already has this figured when he notes that (for example), Intel 4 is only for chiplets while Intel 3 is for complete chips. If so, then regardless of feature sizes, Intel 4 is a reduced size product.
Matters are further complicated by the prospect of multi-sourced chiplets, perhaps assembled in a package provided by someone else. But these are the "problems of success" as someone once put it.
I'm not sure the process labelling gamesmanship is entirely new. I recall from TI that we discovered that our "1um" gate arrays were around half as dense as some other competitor's "1um" gate arrays. Presumably one had sandbagged metal spacing rules and the other more aggressive ones (or something like that).
For what it's worth, my gut says that Intel is essentially doing 3 "real nodes" and 2 "process shrinks" (by my old-fashiobned standards) in 5 years and that this might be a little better than industry average since they likely had a technology pipeline backup after the horrendous 10(7) delays.
Why not simply think of these processes as products (like cars) ? Or call them "platforms" if we must. Intel then offers a range of products targetting various markets. TSMC does the same - but serves a wider range of markets, but is not necessarily a super-set of Intel. What you decide to launch is a combination of your business/marketing strategy, technical capability and resources. These likely vary widely across Intel, TSMC and Samsung. And also a little depending on the size and sophistication of the customers served. It (comparing foundry offerings) is too complex to reduce to simple metrics like process feature sizes anyway.
I think Dan already has this figured when he notes that (for example), Intel 4 is only for chiplets while Intel 3 is for complete chips. If so, then regardless of feature sizes, Intel 4 is a reduced size product.
Matters are further complicated by the prospect of multi-sourced chiplets, perhaps assembled in a package provided by someone else. But these are the "problems of success" as someone once put it.
I'm not sure the process labelling gamesmanship is entirely new. I recall from TI that we discovered that our "1um" gate arrays were around half as dense as some other competitor's "1um" gate arrays. Presumably one had sandbagged metal spacing rules and the other more aggressive ones (or something like that).
For what it's worth, my gut says that Intel is essentially doing 3 "real nodes" and 2 "process shrinks" (by my old-fashiobned standards) in 5 years and that this might be a little better than industry average since they likely had a technology pipeline backup after the horrendous 10(7) delays.
EDA I love that answer, it was more or less what I wanted to say but couldn’t find the words to express. Adding on to your comment on backed up innovation, I think what best exemplifies this is the distance between MTL and ARL. Intel’s first new full node since effectively ICL and a year later they are launching a product with 2 major transistor innovations right after first adopting EUV. A smaller example is intel 3 where the products are launching like 2 quarters later with a claimed P-P improvement of 18%. It isn’t something I think about often, but when I do, I realize just how tall an order “5N4Y” is.
Of course only counting leading edge is doing a disservice to the research happening at the production fabs to make things like 16LL, N6RF, N4X, etc.
Either way, I think now that we are in an era of offering big P-P uplifts on the same node, as well as there no longer being any “one size fits all” nodes; I don’t think I have a problem with this way of doing things. It may not be technically correct, but I do think it does properly show off all the excellent work all of these fabs do and all of the innovation happening beyond smaller wavelengths of light printing smaller features.
If we are just talking leading edge I would say TSMC is on track to do either 4 or 5 “intel equivalent nodes” (N4, N3, N3E/P, and probably N2 assuming we get iPhones in ‘25) in 4 years depending on how you want to label things. But as EDA said nodes are like car models at this point (I think CC also said this back with the 14 vs 16nm debacle). By the metric of there being no metric leading edge TSMC is like 7N4Y.
Of course only counting leading edge is doing a disservice to the research happening at the production fabs to make things like 16LL, N6RF, N4X, etc.
Either way, I think now that we are in an era of offering big P-P uplifts on the same node, as well as there no longer being any “one size fits all” nodes; I don’t think I have a problem with this way of doing things. It may not be technically correct, but I do think it does properly show off all the excellent work all of these fabs do and all of the innovation happening beyond smaller wavelengths of light printing smaller features.
Pat has said in recent interviews that 4 and 20A are internal/chiplet, while 3 and 18A are general with full support for external customers. It is the new tick-tock.
I see the reasoning but it will not help them run the foundries separately and listen to customers if Intel internal remains the primary driver for the major node step. I hope by 20A they will be more outward facing.
TSMC have a similar tick-tock (7 and 6, 5 and 4) but always outward facing, of course.
MKWVentures
Moderator
Obviously 3 and 18A are half nodes or optimization .... But intel getting two nodes out in 4 years would be a great improvement
The real issue with the PR statement is "when does a node become 'delivered'"??
Intel is claiming delivery when no chips are sold? this is similar to what happened on 10nm. Intel 4 is not shipping yet despite it being 'delivered' in Dec 2022.
So lets just keep the metric at "when can the public buy a product with a Chip made by Intel?" this will be 2024 for Intel 3 and Q4 2025 or later for Intel18A if all goes well.
90% of Intel chips sold in 2024 will be Intel 7 or larger (or TSMC made)
I also found the interview with Tom Caulfield entertaining. It is interesting to see how far the talking points are from reality. To be blunt, GF has been good at monetizing the fabs and technology they have acquired. I'm shocked they have not continued to acquire more assets. GF has not been good at developing technology themselves. So yes, it is a good thing GF is not chasing Moore's Law because they sucked at it. The question Mr. Tech Tech Potato should have asked is how are you going to scale your business now that we are seeing a glut of mature technologies? And what about Intel and TSMC putting serious R&D money behind photonics? Does that concern you?
The title for the Tom Caulfield interview is ridiculous, so I expected the content to be terrible. I actually found it to be decent. Questions like Dan suggested would have been good, but this isn't hard hitting journalism. Does GF have enough business for their enhanced legacy nodes, and are those enhancements enough of moat to prevent them becoming generic options? IDK
I slightly disagree. To be a lead customer is something that only intel and Apple really have any recent experience doing. Someone like AMD or Nvidia needs a mature process and design tools/collaterals. Nvidia in particular needs very robust yield for their massive dies. Merchant ARM SOC vendors also probably need excellent yields due to the relatively low ASPs and lack of binning. While I don’t know what the wafer pricing is from TSMC while they are still ramping, but I would assume TSMC isn’t the only one eating the high wafer costs. I would assume Apple is paying a big premium over what they will pay a year later once TSMC’s wafer costs falls dramatically. With all of that, said I would like to see an external customer be the first on an intel node one of these days to prove without a shadow of a doubt intel’s commitment to internal foundry (assuming there is some customer willing to deal with all the bleeding that happens on the bleeding edge). But in the meantime I suppose it is not surprising that customer zero for intel is intel and Apple for TSMC.
I am curious what you think though Tanj. Do you think that other customers would take issue with not getting the process until the whole thing is mature enough for someone like an AMD to design for the node without incident? On paper I don’t see how that is any different than the virtual IDM relationship TSMC and Apple have early in the node development process, but I am not sure if others would see it that way.
You might be a little too hard on GF here Dan. While their track record on node development might be fairly poor, it seems like they’ve finally gotten collaboration down to a T. As an outsider looking in it seems like GF is much better at foundry services than their peers UMC or SMIC who only really try to compete with TSMC on price. Additionally while SOI is niche, GF does make this generally IDM only tech available to fabless firms. Props to GF for seeming to make strides in strengthening the SOI ecosystem and making the tech more mainstream. Is it a strategy that will let them surpass TSMC or Samsung? Not even close. Will it let them be sticky and charge a premium vs SMIC? I think so.
I felt the definition of ‘node’ got cheapened around the ~ 16nm era. I think based on the new definition of ‘node’ that came into being at Samsung and TSMC marketing at the time, Intel IS doing 5 nodes in short order.
TSMC’s naming scheme implies N6 is a different node than N7, where in some previous decades, it would be called a “+”, or not even given a node as the process improved in years past by. (Look how much better Intel’s final 130nm version was in 2003 than its first release in mid-2001). Intel 4 —> 3 seems similar to TSMC N7 —> N6 or. N5 —> N4 in as far as how much has changed.
TSMC’s naming scheme implies N6 is a different node than N7, where in some previous decades, it would be called a “+”, or not even given a node as the process improved in years past by. (Look how much better Intel’s final 130nm version was in 2003 than its first release in mid-2001). Intel 4 —> 3 seems similar to TSMC N7 —> N6 or. N5 —> N4 in as far as how much has changed.
Reminds me of Y2015 when Mark Bohr said that Intel 10nm was on time to be delivered in Y2016.
That was just before Intel started adding many +s to 14nm to show some progress.
What is also ignored is IP for these technologies. Without silicon verified IP -- the technology itself isn't useful. (and obviously external customers will require different IP than Intel internal CPU customers)
tooLongInEDA
Moderator
Credit Intel where it's due: 20A and 18A seem like sensible naming now.
MKWVentures
Moderator
reminder, there is nothing 3nm on Intel3 or N3. There is nothing 18A on Intel18A. 18A . The press refers to nm. the companies do not. TSMC is N7,N5,N4, N3. no nm (please correct me if I am wrong). This is why Intel abandoned the +++ .... to compare to TSMC.
I had hoped that Intel would have a plethora of IP stored up for IFS customers. As it turns out not so much. Customers want commercial IP as that is what they are competing against. So yes IFS has to provide an ecosystem of silicon proven IP but they are working with the top IP companies (Synopsys, Cadence, Arm, etc...) and those folks know how to do it, absolutely. Don't forget that Intel is a top EDA/IP customer so when they call vendors people answer.
If Intel wants to differentiate and win big clients -- they need silicon-demonstrated IP -- on the target Intel process. This would take years from the first phone call to have silicon-proven IP. (could be "a year or even more" after Intel is able to tape-out testchips)
For example, Marvell announced the following 8 months ago. (TSMC 3nm)
"Marvell’s industry-first silicon building blocks in this node include 112G XSR SerDes (serializer/de-serializer), Long Reach SerDes, PCIe Gen 6 / CXL 3.0 SerDes, and a 240 Tbps parallel die-to-die interconnect."
A few months ago, Broadcom showed 200G PAM4 IP -- optical links.
This is the type of IP that has never been Intel's wheelhouse for their CPUs -- and which IFS customers require.