Alphawave Semi will showcase its UCIe chiplets, PCIe and HBM subsystems for AI workloads at booth #720
LONDON, United Kingdom, and TORONTO, Canada – September 25, 2024 – Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, announced it will partner with Arm at this month’s TSMC OIP Ecosystem Forum and present on how to develop terabit AI networks using chiplet architectures.
The TSMC Open Innovation Platform® (OIP) initiative is a comprehensive design technology infrastructure that encompasses critical IC implementation areas to reduce design barriers and improve first-time silicon success. The OIP Ecosystem Forum takes place in Santa Clara, CA, on September 25, with subsequent events in Asia and Europe.
In their presentation entitled ‘Architecting Next-Generation Terabit AI Networks With The Industry’s First Multi-Protocol I/O Connectivity Chiplet’, Letizia Giuliano, VP, IP Product Marketing & Management, Alphawave Semi, and Sridhar Valluru, Director, Product, Technology and Ecosystem Management, Arm, will examine the challenges of deploying AI at scale and the limitations imposed on leading-edge SoCs, before outlining the AI chiplets enabled by UCIe, as well as their use cases. The presentation will take place September 25 at 11:50 a.m. Pacific Time.
This follows a series of announcements by Alphawave Semi on communication protocols relevant to AI SoCs. This includes the first 3 nm UCIe IP with TSMC CoWoS packaging, the tape-out of the industry’s first multi-protocol I/O connectivity chiplet for AI infrastructure, and a partnership with Arm, collaborating on a Neoverse CSS-based CPU chiplet with ultra-high-speed interfaces for AI and HPC infrastructure.
At the TSMC OIP event, Alphawave Semi will conduct a live demonstration of its AresCORE24 UCIe IP, enabling die-to-die communication at 24 Gbps per lane. Additional live demonstrations include a showcase of the company’s MidasCORE3 HBM3E subsystem IP for AI workloads, its PipeCORE128 IP for 128G PCIe 7.0 over Optics, and its ZeusCORE100 112G XLR IP looping back at 128 GT/s.
“The chiplet ecosystem is vital in the advancement of AI SoCs,” said Giuliano. “This approach enables a combination of logic using leading-edge processes, combined with a more cost-effective use of analog circuits, and the adoption of ultra-high-speed connectivity, from SerDes to Ethernet to PCIe. Through our partnership with Arm on this presentation, and the Arm Neoverse CSS-based CPU chiplet, we will demonstrate key learnings that are critical to developing AI technologies.”
Alphawave Semi is a global sponsor of the TSMC OIP Ecosystem Forum events and will be attending all of them. The North America Forum will be followed by events in Japan (October 25), Taiwan (November 6), China (November 13), The Netherlands (November 19) and Israel (November 26).
To register for these forums, please visit https://pr.tsmc.com/english/events/tsmc-events.
To view the event agenda, click this link: https://tsmc-signup.pl-marketing.biz/attendees/2024oip/na/agenda/present.
For more information on Alphawave Semi visit https://awavesemi.com.
About Alphawave Semi
Alphawave Semi is a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: enabling data to travel faster, more reliably, and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com.
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