Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/accellera-day-at-dvcon-u-s-2021.13750/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020470
            [XFI] => 1040170
        )

    [wordpress] => /var/www/html
)

Accellera Day at DVCon U.S. 2021

AmandaK

Administrator
Staff member
Monday, March 1, 2021
Virtual

Join Us for DVCon U.S. 2021!
DVCon U.S. will be held March 1-4 on a virtual platform and will offer attendees a combination of recorded presentations and live Q&A to provide an interactive, high-quality virtual experience.

Keeping with tradition, Accellera Day opens the conference on March 1 with a tutorial, five short workshops, a UVM Birds of a Feather presented by Accellera working groups, as well as an Accellera update and the presentation of the 2021 Technical Excellence Award.

Accellera-sponsored tutorial on Monday, March 1:
Portable Stimulus 2.0 is Here: What You Need to Know” will be presented from 9:00am-11:00am by members of the Portable Stimulus Working Group. Members will share some of the important new features coming in v2.0 of the Portable Test and Stimulus Standard that were added to enhance the usability, programmability, and portability of the standard.

Accellera-sponsored short workshops on Monday, March 1 include:

  • UVM-SystemC Randomization-Updates from the SystemC Verification Working Group” presented from 9:00am-10:00am by members of the SystemC Verification Working Group. The workshop will introduce the basic concepts of UVM-SystemC and show how constrained randomization and functional coverage can be integrated to build a verification environment using the current UVM-SystemC library. Currently, the working group is working on the standardization of a common randomization layer based on CRAVE, a C++ and SystemC constraint randomization library. The workshop will show how constrained randomization can be used within SystemC and integrated into UVM-SystemC verification environments.

  • Getting to Know Accellera’s Emerging Hardware Security Standard: Security Annotation for Electronic Design Integration” presented by members of the IP Security Assurance Working Group from 9:00am-10:00am. This workshop will introduce an emerging new standard called Security Annotation for Electronic Design Integration (SA-EDI) to address security concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to provide information about the IP security relevant to the integrator and recommended mitigations to implement and risk to address. At the conclusion of this session, attendees will better understand risks associated with IP and become familiar with the SA-EDI standard, including how it can be applied and when it will be available for reference.

  • UVM-AMS: A UVM-Based Analog Verification Standard” will be presented by members of the UVM-AMS Working Group from 11:30am-12:30pm. Members will share the work done so far in developing a comprehensive and unified analog/mixed-signal verification methodology based on UVM to improve analog mixed signal and digital mixed signal verification of integrated circuits and systems.

  • Multi-Language Verification Framework Standardization and Demo” will be presented by members of the Multi-Language Verification Working Group (MLVWG) from 11:30am-12:30pm. In this workshop, the MLVWG presents the current status of the proof-of-concept implementation and demonstrates its capabilities. A multi-language example is presented, which combines the UVM library in SystemVerilog and SystemC. Based on this example, the multi-language verification framework, its foundation concepts and the API targeted for standardization is explained and discussed. In addition, multi-language specific UVM standardization requirements will be presented and language extensions will be proposed to address seamless integration and interoperability between UVM verification frameworks in SystemVerilog and SystemC.

  • An Introduction to the Accellera Functional Safety Working Group Standardization Effort” will be presented by members of the Functional Safety Working Group from 11:30am-12:30pm. Accellera formed a working group of functional safety practitioners and experts from the industry to develop a standard that will provide a standardization definition of the Functional Safety data exchange to improve automation, interoperability, and traceability of the implementation of the Functional Safety guidelines and best practices during the lifecycle. The standard plans to capture a data model, language, or format to exchange data seamlessly among functional safety work products and across layers of the supply chain. This workshop presents some of the challenges in the industry for managing the exchange of data related to functional safety and then the goals and mission of the Accellera Functional Safety Working Group towards a new standard to address those challenges.
Accellera-sponsored UVM Birds of a Feather on Monday, March 1 from 10:30am-11:30am:

The Accellera UVM Working Group has recently delivered a UVM library to match the IEEE 1800.2-2020 specification and is now considering which enhancements and bug fixes to work on next that would most benefit the user community. A complication is that many in the user community are still using older versions of UVM and so would not benefit from improvements to the 1800.2-2020 library. This session will gather feedback from the user community through polling and a live Q&A to understand what could be done to help users get to 1800.2-2020 as well as what types of improvements would be the most useful. Attendance to the Birds of a Feather is free, but registration through DVCon is required to access the platform.

Accellera update and presentation of the 2021 Technical Excellence Award:

Following the keynote, at 2:00pm Accellera Chair Lu Dai will give a brief update on Accellera activities and Martin Barnasconi, Accellera Technical Committee Chair, will present the 2021 Technical Excellence Award to this year’s recipient. The Accellera Technical Excellence Award recognizes the tremendous achievements of Accellera Working Group members by selecting outstanding contributors to our standards development processes.

Register for DVCon U.S. 2021 today! DVCon U.S. offers a free registration option that includes access to the keynote, panels, the UVM Birds of a Feather and exhibits.
 
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