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Accellera at the 57th Design Automation Conference

Daniel Nenni

Admin
Staff member
Accellera’s Functional Safety Working Group Addresses Standardization Efforts to Improve Automation, Interoperability, and Traceability

Thursday, July 23
Noon-1:00pm
http://www2.dac.com/events/eventdetails.aspx?id=295-307-

Accellera Systems Initiative, the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, recently formed the Functional Safety Working Group (FSWG). Its mission is to develop a standard to provide a comprehensive and unified definition of the Functional Safety intent to improve automation, interoperability, and traceability across the Functional Safety development lifecycle of electronic circuits and systems.

We invite you to join us for your virtual lunch break as we present an overview of the scope, needs, and goals defined by the FSWG including developments since its formation. Introductions by Lu Dai, Accellera’s Chair, Martin Barnasconi, Technical Committee Chair, and Alessandra Nardi, FSWG Chair, are followed by several informative presentations by functional safety experts focusing on specific perspectives, challenges, and opportunities. You have an opportunity at the end of the presentations to ask questions of the participants during a live Q&A session.

Speakers include: Bala Chavali, AMD; Ghani Kanawati, Arm; Jyotika Athavale, Intel; Franck Galtié, NXP Semiconductors; and Riccardo Vincelli, Renesas.

The lunch break panel is free, but registration through DAC is required to attend. You can register for “I Love DAC” with no fees.

Why Care About IP Security Assurance – What Could Go Wrong?
Tuesday, July 21
1:30-3:00pm

http://www2.dac.com/events/eventdetails.aspx?id=295-29

Organized by IPSA Working Group Chair Brent Sherman, this IP Track Session will discuss Accellera’s emerging IP Security Assurance standard aimed at addressing security concerns in IP. It will also provide a discussion on 3rd-party IP security risks associated with FPGA bitstream integration and key learnings from an IP supplier performing security assurance.

Registration with the Design Automation Conference is required to attend this presentation. Find out more about this session here.

For more information on Accellera at DAC, visit here.

About Accellera
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence; Mentor, A Siemens Business; and Synopsys.

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Accellera and Accellera Systems Initiative are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.

For more information, contact:
Barbara Benjamin
Public Relations for Accellera Systems Initiative
Phone: +1 503 209 2323
Email: barbara@hipcom.com
 
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