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TSMC Begins 2-nm Process Ahead of Samsung, Intel

Daniel Nenni

Admin
Staff member
Samsung, TSMC, and Intel are all in competition to reduce the size of semiconductors,

Samsung, TSMC, and Intel are all in competition to reduce the size of semiconductors

Taiwan’s TSMC, the world’s No. 1 foundry player, has begun developing a 2-nm process, widening its gap with its competitors. As competition for taking the lead in the ultra-fine process has been narrowed down to a three-runner race among TSMC, Samsung Electronics, and Intel, the three are expected to run neck and neck.

On June 6, Taiwanese media outlets and semiconductor industry sources said that TSMC recently began preparations for trial production of 2-nm products for Apple and Nvidia. To develop the 2-nm process, TSMC will send about 1,000 research and development (R&D) personnel to Fab 20 under construction in Hsinchu Science Park in northern Taiwan.

Previously, Samsung Electronics began volume production of 3-nm chips through a gate-all-around (GAA) process in June 2022, six months ahead of TSMC and a world first. Shocked by Samsung’s preemptive strike, TSMC executives publicly revealed their plan for a 2-nm process several times, triggering an ultra-fine fabrication race.

Intel, which announced its plan to re-enter the foundry business in 2021, has also joined the ultra-fine fabrication race. The U.S. semiconductor giant began to expand its presence in the foundry industry by announcing a technical overview, test data, and a roadmap on its wafer backside power supply solution, “PowerVia,” in an online event on June 1 (local time). TSMC is also reportedly developing the technology to deliver power to the back of semiconductors with the goal of using it by 2026.

Intel has set a goal of advancing its foundry process from the current 7-nm range to the 20A (2 nanometer) range in the first half of next year and the 18A (1.8 nanometer) range in the second half. In March, the company laid out a plan to develop a next-generation mobile system-on-chip (SoC) using the 1.8-nanometer process by forging a partnership with ARM. However, there is some pessimism among industry insiders that even if Intel succeeds in the process according to the roadmap, it will be a big challenge for the company to attain the desired yield to break even.

“Samsung is currently one year behind TSMC in 3-nm semiconductor production and two years behind in 4-nm semiconductor production,” said Kyung Kye-hyun, president of the DS Division at Samsung Electronics, in a lecture at KAIST in Daejeon in early May. “Our goal is to catch up with TSMC when TSMC starts a 2-nm GAA process,” Kyung said. Since Samsung Electronics started GAA technology first, the Korean chip maker plans to catch up with TSMC and gain technological advantage over the Taiwanese foundry giant beginning from a 2-nm process to which TSMC will start applying GAA technology.

 
"Previously, Samsung Electronics began volume production of 3-nm chips through a gate-all-around (GAA) process in June 2022, six months ahead of TSMC and a world first. Shocked by Samsung’s preemptive strike, TSMC executives publicly revealed their plan for a 2-nm process several times, triggering an ultra-fine fabrication race."

"Samsung is currently one year behind TSMC in 3-nm semiconductor production and two years behind in 4-nm semiconductor production,”

So in the 3nm semiconductor production, Samsung is "ahead" but "behind " TSMC at the same time.

This is interesting 🤔...
 
We live in a special time, when there are three competing versions of reality, Intel’s, Samsung’s and TSMC’s, everyone is motivated to shape that reality, and there are no corroborating sources. So it’s impossible for the press to obtain a factual perspective.
 
We live in a special time, when there are three competing versions of reality, Intel’s, Samsung’s and TSMC’s, everyone is motivated to shape that reality, and there are no corroborating sources. So it’s impossible for the press to obtain a factual perspective.

In each of their own "Meta-World" they can all be correct can they not?

Isnt this what the multiverse is all about?
 

"TSMC did not comment on specific details in response to the report, but stated that the development of 2nm technology is progressing well and aims to hit mass production by 2025."

"In the initial stages, TSMC will set up a small trial-production line at its Hsinchu headquarters, with a target of taping out around 1,000 2nm chip pieces by the end of this year, the report said."


Must be heavy on multipatterning (no HNA EUV installed this year).
 
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"TSMC did not comment on specific details in response to the report, but stated that the development of 2nm technology is progressing well and aims to hit mass production by 2025."

"In the initial stages, TSMC will set up a small trial-production line at its Hsinchu headquarters, with a target of taping out around 1,000 2nm chip pieces by the end of this year, the report said."


Must be heavy on multipatterning (no HNA EUV installed this year).
It all depends how TSMC N2 compares to N3. From what I've seen I believe it's basically a similar metal stack (slightly reduced pitches) but with new transistors dropped in underneath -- GAA instead of FinFET, like TSMC 16nm dropped in FinFETs instead of planar MOS in 20nm -- then it won't be much heavier on multipatterning than N3. Increased gate density comes mainly from smaller footprint transistors and other DTCO measures not tighter pitches.
 
Lets see who has a product first. this Manufacturing ready and pre-production is getting annoying. Intel is planning its first Intel 3 (there is nothing 3nm about it) product to launch in June 2024. I believe the plan is for 20A Product in Jan 2025 (product launch best case). I am sure they will announce "manufacturing ready" long before any product is shipped. Intel has also stated it will run multiple internal products on a node before production for foundry products.... so lets see.

My bet would be on TSMC shipping N2 in production before the others ... . Is there betting in Vegas on first chip in a production device?

TSMC 1:1, Samsung 2:1, Intel 2:1 ..... Rapidus 2875624 : 1
 
Lets see who has a product first. this Manufacturing ready and pre-production is getting annoying. Intel is planning its first Intel 3 (there is nothing 3nm about it) product to launch in June 2024. I believe the plan is for 20A Product in Jan 2025 (product launch best case). I am sure they will announce "manufacturing ready" long before any product is shipped. Intel has also stated it will run multiple internal products on a node before production for foundry products.... so lets see.

My bet would be on TSMC shipping N2 in production before the others ... . Is there betting in Vegas on first chip in a production device?

TSMC 1:1, Samsung 2:1, Intel 2:1 ..... Rapidus 2875624 : 1

Personally I think most customers will stay with N3 for a generation or two and wait for the second or third generation of N2. Not just cost, also the design ecosystem needs to catch up.

Apple, NVDA, AMD, QCOM will probably jump to N2 with Apple being the first HVM N2 customer in 2026 (my guess).
 
Lets see who has a product first. this Manufacturing ready and pre-production is getting annoying. Intel is planning its first Intel 3 (there is nothing 3nm about it) product to launch in June 2024. I believe the plan is for 20A Product in Jan 2025 (product launch best case). I am sure they will announce "manufacturing ready" long before any product is shipped. Intel has also stated it will run multiple internal products on a node before production for foundry products.... so lets see.

My bet would be on TSMC shipping N2 in production before the others ... . Is there betting in Vegas on first chip in a production device?

TSMC 1:1, Samsung 2:1, Intel 2:1 ..... Rapidus 2875624 : 1
Rapidus part make me laugh out loud. I know its far too early but has anyone heard anything about TSMC N2 that is not from TSMC. I'd like to know much more on how it's progressing and how people expect it to match up against 18A
 
TSMC taking a more conservative approach as usual. 2nm will be first GAA for them but will not use high NA so there will be multi patterning. This is consistent with TSMc approach to derisk one new technology at a time.

It will be a high cost, short lived node that will probably only appeal to a small subset of customers.

Intel will probably have some advantage initially since they will be using high NA out of the gate, but there is more risk to that approach.

Any advantage Intel gets initially with 18A will fade quickly however.
 
Rapidus part make me laugh out loud. I know its far too early but has anyone heard anything about TSMC N2 that is not from TSMC. I'd like to know much more on how it's progressing and how people expect it to match up against 18A
tsmc: Pathfinding --> R&D --> Fab
The latest news should mean that N2 is leaving the R&D phase and the Fab team starts to take over.
 
TSMC taking a more conservative approach as usual. 2nm will be first GAA for them but will not use high NA so there will be multi patterning. This is consistent with TSMc approach to derisk one new technology at a time.

It will be a high cost, short lived node that will probably only appeal to a small subset of customers.

Intel will probably have some advantage initially since they will be using high NA out of the gate, but there is more risk to that approach.

Any advantage Intel gets initially with 18A will fade quickly however.
Intel reportedly pulled in 18A without HNA as well https://www.tomshardware.com/news/intel-completes-development-of-18a-20a-nodes. Their SPIE paper Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node is also without HNA.

Actually this decision shouldn't be too much of a surprise. The EUV community was already aware of the reduced depth of focus of the High-NA EUV system. This is a known trend for a given wavelength. But what is more severe this time is more aggravated stochastic effects, because even fewer photons are absorbed. I had discussed this elsewhere: Enhanced Stochastic Imaging in High-NA EUV Lithography.

This year at SPIE a vendor disclosed the sensitivity of the thin EUV resist to secondary electrons from underlying layers: Fundamentals of EUV stack for improving patterning performance. This is a new fundamental effect to be studied. So it is definitely a more straightforward decision not to wait.
 
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TSMC taking a more conservative approach as usual. 2nm will be first GAA for them but will not use high NA so there will be multi patterning. This is consistent with TSMc approach to derisk one new technology at a time.

It will be a high cost, short lived node that will probably only appeal to a small subset of customers.

Intel will probably have some advantage initially since they will be using high NA out of the gate, but there is more risk to that approach.

Any advantage Intel gets initially with 18A will fade quickly however.

I suspect most TSMC N2 customers will wait for the 2nd generation N2 process with backside power (like Intel 18A), which will also have much more in common with the nodes that will follow.

Apart from having better performance for both signals and power (and higher density), the layout of IP libraries/blocks/chips with BPD will be *very* different, and I can't see many people being willing to pour a huge amount of effort into the non-BPD-N2 which is effectively a dead-end process -- unless they just port from N3 and swap transistors to minimize cost/effort/TTM, and save major rework for N2 Gen2 and what follows.

This may also mean TSMC have to try and pull N2 with BPD in, both to compete with Intel and encourage customers to switch to N2 instead of sticking with N3.
 
I suspect most TSMC N2 customers will wait for the 2nd generation N2 process with backside power (like Intel 18A), which will also have much more in common with the nodes that will follow.

Apart from having better performance for both signals and power (and higher density), the layout of IP libraries/blocks/chips with BPD will be *very* different, and I can't see many people being willing to pour a huge amount of effort into the non-BPD-N2 which is effectively a dead-end process -- unless they just port from N3 and swap transistors to minimize cost/effort/TTM, and save major rework for N2 Gen2 and what follows.

This may also mean TSMC have to try and pull N2 with BPD in, both to compete with Intel and encourage customers to switch to N2 instead of sticking with N3.
I was initially of this mind too, add in the poor density scaling of vanilla N2 and I figured people would just rather wait a year for the more substantial upgrade given all the design dollars that would need to be spent. Now I am not as sure. TSMC earlier this year mentioned:
Part of the TSMC N2 technology platform, a backside power rail provides additional speed and density boost on top of the baseline technology.
  • The backside power rail is best suited for HPC products and will be available in the second half of 2025.

That wording makes it sound like N2P will have a FSPD version with the BSPD version being the headline feature for the HPC flavor of N2P and the base version of N2X. If that is indeed the case this seems like a curious decision. I have to believe that mobile would also so benefits, and splitting their design ecosystem like that also seems like a bad idea. But I might (and probably am) just be reading too far into it, and maybe everything beyond base N2 will have a BSPDN.
 
I was initially of this mind too, add in the poor density scaling of vanilla N2 and I figured people would just rather wait a year for the more substantial upgrade given all the design dollars that would need to be spent. Now I am not as sure. TSMC earlier this year mentioned:


That wording makes it sound like N2P will have a FSPD version with the BSPD version being the headline feature for the HPC flavor of N2P and the base version of N2X. If that is indeed the case this seems like a curious decision. I have to believe that mobile would also so benefits, and splitting their design ecosystem like that also seems like a bad idea. But I might (and probably am) just be reading too far into it, and maybe everything beyond base N2 will have a BSPDN.
I see a clear dividing line between N2/FSPD and N2P/BSPD -- in terms of design/layout/tools N2 is the last member of the FSPD family (including N3) with GAA dropped in instead of FinFETs (like 16nm), N2P/BSPD is the first member of the next-generation processes -- for customers the design/layout/simulation consequences (time/effort/cost) of shifting to BSPD are *way* bigger than shifting to GAA, though both are a big challenge for the TSMC process teams.

The biggest beneficieries of BSPD may indeed be HPC initially -- not just the CPU cores but also accelerators and high-speed SERDES -- but once BSPD is established and debugged I can't see mobile staying with FSPD because speed and power consumption are both improved with BSPD.

Exactly how TSMC are going to approach this is closely guarded, and may well change depending on how the Intel and Samsung processes go -- for example if Intel do succeed with BSPD (and getting 20A/18A into high-yielding mass production, good luck with that...) it will put TSMC at a major disadvantage for HPC, and they may be forced to introduce BSPD before they would really like to.
 
Exactly how TSMC are going to approach this is closely guarded, and may well change depending on how the Intel and Samsung processes go -- for example if Intel do succeed with BSPD (and getting 20A/18A into high-yielding mass production, good luck with that...) it will put TSMC at a major disadvantage for HPC, and they may be forced to introduce BSPD before they would really like to.
At this point whatever TSMC is doing, the die has been cast. People must already be designing for N2 as we are already about 2 years out from N2 iPhone HVM and 3 years out from Tier-2 customer HVM on N2P. TSMC telling a MDTK or QCOM next year to drop their design work on FSPD because 20A products launched in 24 and 18A ones launched in 25 in reasonable volumes at good PPWs would be a great way to undo decades of work building a reputation as being customer obsessed.
 
At this point whatever TSMC is doing, the die has been cast. People must already be designing for N2 as we are already about 2 years out from N2 iPhone HVM and 3 years out from Tier-2 customer HVM on N2P. TSMC telling a MDTK or QCOM next year to drop their design work on FSPD because 20A products launched in 24 and 18A ones launched in 25 in reasonable volumes at good PPWs would be a great way to undo decades of work building a reputation as being customer obsessed.
That's not what I said. They won't drop FSPD, they'll bring forward BSPD and offer both, FSPD for customers who prioritise lower risk/higher yield and BSPD for those who prioritise PPD. It's what they've done for years with process variants and "half-node" steps. It's quite possible they already have two plans/roadmaps internally, one for if Intel fail (carry on as now with later BSPD in N2 V2) and one for if Intel succeed (release BSPD earlier) -- because one thing TSMC are very good at is planning... ;-)

(and if they do pull BSPD in it might be done on the quiet for limited critical customers only who they don't want to lose to Intel -- maybe only one...)
 
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Intel will probably have some advantage initially since they will be using high NA out of the gate, but there is more risk to that approach.

Any advantage Intel gets initially with 18A will fade quickly however.
Note, Intel has said in the past, 18A will be ready before High NA EUV is available. Even it is, it's not sufficient enough to cover the wide spectrum of products Intel needs to deliver in 2025
 
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