Intel Details PowerVia Chipmaking Tech: Backside Power Performing Well, On Schedule For 2024
- Thread starter Brady
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I was on that call as was Scott Jones. He will offer his perspective soon. In the comment section of this article:
As far as the rest of the world goes
https://www.imec-int.com/en/articles/imec-demonstr...
Points being
- imec (and through them, essentially TSMC and SS) have already demonstrated this tech in 2021. This includes Intel's precious nanoTSV's that they're trying hard to pretend are tech exclusive to them. What's known of TSMC is that their roadmap starts with BSPDN but NOT nano-TSV's, that's for a year later; but that reflects TSMC's usual caution, one step at a time; rather than they don't know about nTSV's or can't manufacture them.
- the big win with BSPDN is not the power/voltage droop improvements. Those are nice, but only matter if you're already driving your chip at crazy power levels. No, the big win is relieving routing congestion in M1. It is this routing congestion that has throttled the down-scaling of SRAM in recent processes; and the expectation is that by moving to BSPDN (even the initial, simpler, non-nTSV version chosen by TSMC for gen1) SRAM scaling can resume. BUT for that to be of value, you have to be willing to keep the rest of your metal network in place, as low-pitch as before...
In other words, the issue is not "Intel smart, TSMC stupid"; it is priorities.
Intel's priority (for better or worse) it to be able to crank up the *effective* power and frequency of their chips even more. For them, right now, BSPDN matters insofar as it allows for slightly lower power translated into slightly higher clock.
TSMC's priorities are (a) process implementation reliability [hence two stages, BSPDN first, nTSV second a year later] and (b) denser SRAM (which they get some of, even at the first stage of BSPDN without nTSV).
IMHO the longer-term imec/TSMC strategy will also move clocks down to the backside. This will have little effect on power, but it will relieve routing even more, allowing for even denser SRAM. I have no idea, but I would not be surprised if at least part of the slow cautious TSMC strategy is to put together a process that naturally extends to moving the clocking layers to the backside, whereas the faster Intel strategy has been to ignore this and hope that, somehow, it can be retrofitted in the future.
BOTTOM LINE: Intel's implementation is based on Intel internal usage. TSMC's implementation will be based on foundry customer usage which is a very different thing.
name99 - Monday, June 5, 2023 -
As usual from an Intel presentation, you get an accurate (kinda...) story about what INTEL is doing, and a completely distorted story about how this relates to the rest of the world.As far as the rest of the world goes
https://www.imec-int.com/en/articles/imec-demonstr...
Points being
- imec (and through them, essentially TSMC and SS) have already demonstrated this tech in 2021. This includes Intel's precious nanoTSV's that they're trying hard to pretend are tech exclusive to them. What's known of TSMC is that their roadmap starts with BSPDN but NOT nano-TSV's, that's for a year later; but that reflects TSMC's usual caution, one step at a time; rather than they don't know about nTSV's or can't manufacture them.
- the big win with BSPDN is not the power/voltage droop improvements. Those are nice, but only matter if you're already driving your chip at crazy power levels. No, the big win is relieving routing congestion in M1. It is this routing congestion that has throttled the down-scaling of SRAM in recent processes; and the expectation is that by moving to BSPDN (even the initial, simpler, non-nTSV version chosen by TSMC for gen1) SRAM scaling can resume. BUT for that to be of value, you have to be willing to keep the rest of your metal network in place, as low-pitch as before...
In other words, the issue is not "Intel smart, TSMC stupid"; it is priorities.
Intel's priority (for better or worse) it to be able to crank up the *effective* power and frequency of their chips even more. For them, right now, BSPDN matters insofar as it allows for slightly lower power translated into slightly higher clock.
TSMC's priorities are (a) process implementation reliability [hence two stages, BSPDN first, nTSV second a year later] and (b) denser SRAM (which they get some of, even at the first stage of BSPDN without nTSV).
IMHO the longer-term imec/TSMC strategy will also move clocks down to the backside. This will have little effect on power, but it will relieve routing even more, allowing for even denser SRAM. I have no idea, but I would not be surprised if at least part of the slow cautious TSMC strategy is to put together a process that naturally extends to moving the clocking layers to the backside, whereas the faster Intel strategy has been to ignore this and hope that, somehow, it can be retrofitted in the future.
BOTTOM LINE: Intel's implementation is based on Intel internal usage. TSMC's implementation will be based on foundry customer usage which is a very different thing.
So is it correct to say the “not invented at Intel” issue they claim to be fixing by moving to standard design flows for IFS is… not so fixed, yet? Or at least they’re still learning/ramping up on what being a foundry really means (for customers)?
Seems like great innovation either way, and I hope it gives them at least some edge in the Foundry space… they’re going to need it.
Seems like great innovation either way, and I hope it gives them at least some edge in the Foundry space… they’re going to need it.
I think it will give them an edge against AMD, not so much TSMC. Maybe it will convince AMD to use IFS? Just kidding, I never see that happening.
Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node
This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers...
I've got to respectfully disagree with you Dan. Based on this and prior disclosures, I think this is very foundry aware integration scheme. At SPIE where intel talked about how foundry customers were the ones specifically asking for direct print metal layers on 18A. Besides this showing at least some degree of a customer first mindset, wouldn't the simplified DRs that this could enable make the barrier for entering the IFS ecosystem smaller than if they ballooned process complexity with MP? Based on how the ecosystem is the make or break thing for IFS, to me, making an easy to design for node and using it to rapidly scale the intel ecosystem sounds WAY more important than closing the HD SRAM density gap that exists between current intel/TSMC nodes. Besides the direct print angle, backside power also sounds like it will be a simplification for designers once they get used to it (but I could be wrong on that point as I am not a chip designer). Besides the ease of use argument, as Fred has noted ad nauseam, relaxing the pitches on the lowest metal layers allows for lower doses (ie more wafers per stepper per hour). To me these all sound like things that benefit IFS and it's customers. After all IFS is a foundry that is starting from literally 0, as such I think conservatively picking one's battles is a prudent move. As far as I know there is no confirmation what back side power delivery scheme TSMC is even using. However if TSMC does end up using a buried power rail, my point is not that this approach is bad. My point is more so that 18A family and N2P are different designs, coming out at different times, and from firms with different strategic positions. To me it makes sense that they would have different optimization points. Of course this is just my 2 cents.
With PowerVia, Intel Achieves a Chipmaking Breakthrough
Intel’s Ben Sell explains how the company developed and proved the world's first backside power solution, taking a major step forward in chipmaking.
www.intel.com
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The SPIE paper 1229202 talks about bidirectional direct print for flexibility, but at their reference 32 nm pitch, there is essentially no pupil space for supporting bidirectional.Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node
This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers...www.spiedigitallibrary.org
At SPIE where intel talked about how foundry customers were the ones specifically asking for direct print metal layers on 18A. Besides this showing at least some degree of a customer first mindset, wouldn't the simplified DRs that this could enable make the barrier for entering the IFS ecosystem smaller than if they ballooned process complexity with MP? Based on how the ecosystem is the make or break thing for IFS, to me, making an easy to design for node and using it to rapidly scale the intel ecosystem sounds WAY more important than closing the HD SRAM density gap that exists between current intel/TSMC nodes. Besides the direct print angle, backside power also sounds like it will be a simplification for designers once they get used to it (but I could be wrong on that point as I am not a chip designer). Besides the ease of use argument, as Fred has noted ad nauseam, relaxing the pitches on the lowest metal layers allows for lower doses (ie more wafers per stepper per hour). To me these all sound like things that benefit IFS and it's customers.
With PowerVia, Intel Achieves a Chipmaking Breakthrough
Intel’s Ben Sell explains how the company developed and proved the world's first backside power solution, taking a major step forward in chipmaking.
Even if it is unidirectional doesn’t direct print still simplify work for designers in addition to the cost incentive? And if you don’t mind me asking your opinion, at what pitch would you say that bidirectional seems feasible with the current lithographic toolkit?
A unidirectional pitch would need cuts generally; for the 0.33 NA you would need to be about 36 nm pitch to get bidirectional.
34 nm pitch still similar to 32 nm (negligible overlap between X and Y):
For true 2D routing at these lower pitches, you would need grid-based routing for SAQP or SADP: https://www.linkedin.com/pulse/application-specific-lithography-28-nm-pitch-routing-frederick-chen
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I was tempted to call it a "1.5D" or "1.3D"
Cute.I was tempted to call it a "1.5D" or "1.3D"
But if it delivers advantage, it adds value. I can see that making a 1.5D wiring layer would offer significant advantages, especially coupled with clever library design. The bigger question will be the quality of EDA support.
jorgequinonez
New member
Be skeptical: I would doubt anything Intel says, given their history of overpromising and under delivering.
Not sure, possibly the existing unidirectional layers already do this?
Followup: This style, which should be considered a unidirectional variant (the same dipole illumination is used), was already disclosed by ASML more than 20 years ago. https://www.spiedigitallibrary.org/...ng-dipole-illumination/10.1117/12.425215.full The paper also discusses the limitations of this approach.
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What is old is new again. A mixed blessing of being a captive foundry is that their colleagues making CPUs and GPUs may be willing to lean in and work within the limitations to extract advantage. Will their open foundry customers do the same? As I said, it will come down to EDA. The EDA of today is far more capable than 20 years ago, and as you point out the pattern is known in DUV so may already have been coded into layout algorithms.
ASML does not need EUV to be ideal, making perfect patterns on single exposure. It just needs it to give better results with all the existing trickery customers learned from the DUV era. So long as throughput is sufficient, customers experience it as advancing.