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I wouldn't say that verilog is poor as an entry language. Do you know how to design complex async automata (not a Moore/Mealy FSM)? the entry is just a wave form. A sequence of signal transitions on the paper. You need to take this waveform as an entry, than to draw a corresponding Petri net...
Thanks for sharing! A quite interesting news. At the first glance they are making just another Amulet/HS chip, but with dynamic power control. Hope I am wrong
Do you mean, you are experimenting with Async automata? And, you are planning to implement it in FPGA using bundled delay (BD) approach...
4 years have passed and I am at a crossroads again (looking for work). Has anything changed on the Async field? Any new commercial async-involved projects appeared?
Recently I saw a German project where AI (reconfigurable SNN) chip is based on purely async neurons and a serving NoC that...
Hi! I have been working as a hardware developer (both F-End and B-End digital flow) for many years. My hobby is so-called self-timed (asynchronous, QDI) logic. Last 3 years I spent learning the ways to use Cadence and Synopsys synthesizers and B-End tools for async implementations, and I made...