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  1. C

    I would like to know the approach using by tsmc , samsung , intel for SADP process ?

    For lower nodes like 10nm and 7nm , foundries are using SADP process for processing of Mx layers . I would like to know what is the approach using by tsmc/samsung/intel for these SADP layers ? The various approaches are 1. Traditional SID-SADP (Block Mask) 2. Mandrel Fill/Cut Mask SID-SADP...
  2. C

    why poly(transistor gate) orientation check is significant in leading edge tech

    what is the reason behind poly (transistor gate) orientation check in advanced process nodes ? Basically the check is like all the standard cells , memories , IP's need to have same poly orientation ( either horizantal or vertical ) . why not to use both orientations ?
  3. C

    what is reason for not allowing Mixed VT cells in a chip for FDSOI technology ?

    Hi In 22nm fdsoi technology , there were some design rules like VT spacing between SVT and LVT , SVT and HVT std cells so it is not possible to allow mixed VT in a chip . I want to know what was the reason for this ? is there any limitation from Manufacturing point of...
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