You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
My guess for earliest intercept is launching the M4 with a launch during the summer (with the large die ultra and max chips coming at a later time like with M2). Option two is the 2026 iPhone. TSMC mentioned how brutal the process flow durations are getting, so it would not surprise me if Apple...
Probably because memory is the ugly stepchild of the semi industry. It is a sad fate since no memory means the logic is completely worthless, but good luck making any technical arguments to commerce. As for intel in particular they are also building more factories in the US than Micron 5+1...
Not using EUV for 10nm was (and even with the benefit of hindsight still is) objectively the correct decision, no ifs thens or buts. Even if ASML had the tools in 2018 to fully equip intel at the expensive of Samsung and TSMC for volume production in 2019 (Icelake), then 10nm would have been...
My guess is they were expecting more. Being up double digits is kind of the expectation for a firm that has grown every year since it’s inception with the exception of 2023. A similar deal happened with NVIDIA’s last call where they were up a good bit but stock stayed flat because the...
We will have to see what the scale of this R&D is, but this is potentially very interesting/a big shake up. I have to assume that TD will still be done in Hwaseong for logic and memory. But maybe they will alternate logic TD between Korea and Texas (similar to what Micron seem to do with DRAM TD...
Could you give some examples? My understanding is that everything was just serial numbers for a while (4004, 8088, 286, 486, etc) before moving to things in Oregon (Tualatin, Willamette, etc), and finally I assume the current lakes and rapids aren't all in Oregon.
That is derivative nodelet. TSMC almost never converts fabs to new process technologies, they almost always build new fabs for new process node families. The only exceptions in TSMC company history are 20nm fabs since that technology didn't gain widespread adoption, 10FF for the same reason...
TSMC isn't intel was the one who built an advanced packaging fab in the US. Thanks for pointing this out since the wording was terrible, I fixed the comment for clarity.
TSMC is getting 78% the money as intel while intel builds 1.67X more fabs in the US + an advanced packaging site. The US has it's national champion and their based in the based in Hsinchu (part of the mythical 51st state of the ROC) :ROFLMAO:. Jokes aside this is super cool to see. I'm happy to...
Kind of insane that intel is as close to TSMC as they are. I expected it to be a larger gap given intel lacks the free money printers (aka old depreciated fabs). While 2021 is the most extreme year, to think that back in 2021 intel wafer demand (on a dollar basis) was like 30-40% of all of...
Excuse my ignorance Ian, but I guess a few questions. The way NVIDIA makes their new product more valuable than the old one is improving the flops/$, yes? If so then I assume we would agree that the best way to increase the number of flops/$ is to increase energy efficiency because over the...
This is a far too simplistic way of looking at it IMO. TSMC mobile process and HPC are not the same. A phone SOC needs ultra low leakage to maximize battery life and they pay for that with higher active power consumption. HPC wants the best performance in a given power envelop. Intel client CPUs...
If intel's cost per wafer is 2x than TSMC, the cost of goods sold literally can't increase for product side like it did. If cost was even 1% greater than price COGS would go down. Later on they even say they are charging about 0% margin for intel 7 vs N5 wafer price. So let's call 10nm cost = N5...
Yeah I thought that was weird too. Only guess I have as to why is that D1X mod 3 finished and Fab34 finished so they would have been installing new tooling for those? Could also be related to increased to getting to a more expensive phase of TD?
Agreed, I knew there would be a loss but I had assumed it would be more minor than what it is. But seeing the 2022/21 data I suppose there is at least some sollice in about a third of the operating loss being due to fabs being underutilized because intel overshot their product demand...
They have mentioned a few times based on the PPA of the best node. One thing they hinted at on this call was charging "leadership prices" for 18A wafers, which tracks with where they want to be with 18A. In a statement I find somewhat conflicting they also mentioned undercutting TSMC to gain...
They said they were comparing to the best node on the market at the time. Given ICL launched at EOY 2019 and TGL at EOY 2020, and they said intel 7 was far behind on density and performance it is pretty clear they are comparing to N5 family not N7. Density wise intel 4 trades blows with N5...
To once again reprise my role as the devil's advocate, what is the alternative if you want a national champion for advanced CMOS logic? SMIC is lagging even intel 10nm by 4+ years to market even with rampant TSMC/Samsung poaching and an effectively infinite budget. I can't think of any other way...
Ann K (and I think even Pat) has mentioned this in some of the previous interviews she has done. Back in the old day intel would say "Hey just drop the tool off at the dock and we will take care of the rest". From there they would cut the vendors out of the loop because A. they didn't want to...
It's the china times I doubt they have any clue what they are talking about. Considering N2 is almost certainly using the same metal stack and CPP as N3 (or more likely N3E), the only thing they could possibly be talking about (assuming they aren't just totally making things up) is higher...
