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Banned
I was reading an article about TSMC's challenges in advanced packaging, their VP explained that "when it comes to advanced packaging, it is still stuck at 2μm...cost control and efficiency become a hurdle when TSMC uses frontend equipment, such as those for copper interconnect process, to facilitate heterogeneous integration."
This part confuses me...what does the 2μm refer to here? As I understand, heterogenous integration basically integrates various chips of different nodes, so this doesn't make much sense to me. Article is below
This part confuses me...what does the 2μm refer to here? As I understand, heterogenous integration basically integrates various chips of different nodes, so this doesn't make much sense to me. Article is below
TSMC’s 3nm Enters Pilot Production, but Advanced Packaging Faces Challenges
TSMC has announced that its cutting-edge 3nm process has entered pilot production. Volume production[...]
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