Industry faces “acute” CPU shortage with hope that Intel 18A yields improve

[MKWVentures]

Just my opinion .... and from the view of a potential customer:

1) Roadmap & timeline trust factor
2) Competitive IP concerns
3) Infancy of the use of industry standard tooling

I suspect that many people focus on the competitiveness in the metrics between Intel and TSMC (which is quite normal for a bunch of engineers ).

Once a pilot program is actually in progress, I suspect that other issues will arise that a customer didn't think as much about in the beginning. Issues like the issue process, corrective action process, contractual issues, support structure, etc are things that lots of people overlook in the beginning of a major program, but that hurt like crazy once you are in the middle of it all.

One thing to ask: Is the Intel Product group happy with IFS as a supplier right now? Are they happy with the supply and planning and delivery? How do they score IFS vs TSMC as a supplier?

 

[siliconbruh999]

One thing to ask: Is the Intel Product group happy with IFS as a supplier right now? Are they happy with the supply and planning and delivery? How do they score IFS vs TSMC as a supplier?

this is going to have internal politics involved tbh depending on who you ask and i think we should let products decide in the roadmap.

 

[OneEng]

One thing to ask: Is the Intel Product group happy with IFS as a supplier right now? Are they happy with the supply and planning and delivery? How do they score IFS vs TSMC as a supplier?

While I think that is a good metric to consider, I would have concerns about how the internal customer's opinion relates to an external customer's opinion.

It has been my experience that people that are used to having an internal supplier tend to be very critical of the internal supplier ..... until they deal with an external supplier. Also, the financial politics are strong with an internal supplier (who get's the lion's share of the profit?) vs. an external supplier.

I would be very interested to hear how Intel Product group rates IFS vs TSMC though.

 

[MKWVentures]

While I think that is a good metric to consider, I would have concerns about how the internal customer's opinion relates to an external customer's opinion.

It has been my experience that people that are used to having an internal supplier tend to be very critical of the internal supplier ..... until they deal with an external supplier. Also, the financial politics are strong with an internal supplier (who get's the lion's share of the profit?) vs. an external supplier.

I would be very interested to hear how Intel Product group rates IFS vs TSMC though.

Intel has been using TSMC for some time now. Billions in spending per year. multiple products, This is why you should always have multiple vendors and a internal vs Exterrnal discussion on each project.

I agree everyone is very critical of Internal supplier. Some external suppliers are better than Intel Internal, some are problematic,

in the Past MJ and even PG were clear that product group decides... no "take one for the team". That how the whole IDM2.0 got agreed upon

 

[OneEng]

Intel has been using TSMC for some time now. Billions in spending per year. multiple products, This is why you should always have multiple vendors and a internal vs Exterrnal discussion on each project.

I agree everyone is very critical of Internal supplier. Some external suppliers are better than Intel Internal, some are problematic,

in the Past MJ and even PG were clear that product group decides... no "take one for the team". That how the whole IDM2.0 got agreed upon

One could argue that Intel's "5 nodes in 4 years" was a bit of a tap dance ..... and that they didn't do anything like that.

"Intel 7" was just renaming 10nm superfin. Intel 4 and 3 were most certainly a node change as Intel finally got EUV working, BUT really Intel 3 was just a good library tweak (and a few other things) to Intel 4. Then Intel completely dropped 20A and the original roadmap had 18A being released in 2H 2024.

So realistically speaking, what Intel ACTUALLY got done was 3 nodes (Intel 4, Intel 3, 18A) from July 2021 to Jan 2026. So 3 nodes in 4.5 years. Still, not bad.

BUT, that same presentation stated that Intel would RETAKE foundry leadership from Intel at 18A. As of today, N2 is 31% more dense than 18A and is more power efficient (which is a big deal for DC processors).

I would argue that Intel DID make up ground and is at least in the ball park; however, the cost was substantial. 18A and 18A-P are most definitely a make or break moment in Intel history.

Despite my negative review of the situation, I really am pulling for Intel. I consider them critical to the USA from a geopolitical standpoint.

 

[user nl]

While I think that is a good metric to consider, I would have concerns about how the internal customer's opinion relates to an external customer's opinion.

It has been my experience that people that are used to having an internal supplier tend to be very critical of the internal supplier ..... until they deal with an external supplier. Also, the financial politics are strong with an internal supplier (who get's the lion's share of the profit?) vs. an external supplier.

I would be very interested to hear how Intel Product group rates IFS vs TSMC though.

Yes, the grass always seems greener at the other side.

However, the key issue with Intel is that even if Product has their silicon made at the other side, the profit that they make with this does not flow to Product, but to Foundry. That is the lack of positive energy/feedback from this joint operation of Product & IFS.

It is hard to beat the law of "necessity of running large numbers of wafers in Semi-Fab manufacturing". That law seems quite universal, independent of management and geography, valid in Taiwan, USA and Korea.....

Indeed, because IFS is a US National Security asset, Intel Product "has to accept" that their profit is not for themselves (bonus, shares, intellectual freedom and competition etc) but to keep IFS from sinking down a quicksand area.......

 

[Xebec]

BUT, that same presentation stated that Intel would RETAKE foundry leadership from Intel at 18A. As of today, N2 is 31% more dense than 18A and is more power efficient (which is a big deal for DC processors).

What are the source(s) for N2 being more power efficient than 18A?

IIRC 18A is generally cited as the highest performance of the two nodes, but efficiency is very dependent upon what clock speed you're going for, etc. the SRAM charts Intel and TSMC showed seem to favor 18A at mid to higher frequencies. (0.8V - ~ 3.3 GHz for TSMC N2, and ~ 4.2 GHz for 18A). (I understand SRAM is different than logic..)

 

[OneEng]

What are the source(s) for N2 being more power efficient than 18A?

IIRC 18A is generally cited as the highest performance of the two nodes, but efficiency is very dependent upon what clock speed you're going for, etc. the SRAM charts Intel and TSMC showed seem to favor 18A at mid to higher frequencies. (0.8V - ~ 3.3 GHz for TSMC N2, and ~ 4.2 GHz for 18A). (I understand SRAM is different than logic..)

View attachment 4548View attachment 4549

I think there are multiple sources on the density aspect of the comparison. There is one Here from Jan 2026 with this quote:

TSMC said its 2-nm tech will lead the chip industry in density and energy efficiency.

... but this is TSMC saying it.

Intel does have a track record of making transistors that can clock high though. I do wonder about the hot spot issues discussed in some threads here causing the overall design to need to clock lower because of this, but really that is just my wild speculation.

Another pro for Intel is exactly the fact that 18A is less dense than N2. Generally speaking in engineering "You don't get something for nothing". It is possible that Intel has intentionally given up some density in order to be more power efficient. Rumors are that Zen 6 on N2 will clock to around 6.3-6.4Ghz (with some wild crazy people shouting 7Ghz). I wonder if Intel is aiming at higher clocks, or more power efficiency. I am definitely NOT used to the idea that Intel doesn't have the most transistor density. Spent decades following this technology where Intel lead the entire industry .... sometimes by double the density.

Anyway, the answer for you is that my evidence is pretty slim .

 

[siliconbruh999]

Another pro for Intel is exactly the fact that 18A is less dense than N2. Generally speaking in engineering "You don't get something for nothing". It is possible that Intel has intentionally given up some density in order to be more power efficient. Rumors are that Zen 6 on N2 will clock to around 6.3-6.4Ghz (with some wild crazy people shouting 7Ghz). I wonder if Intel is aiming at higher clocks, or more power efficiency. I am definitely NOT used to the idea that Intel doesn't have the most transistor density. Spent decades following this technology where Intel lead the entire industry .... sometimes by double the density.

Clock speed shouldn't be a metric to judge design Intel 7 Raptor Lake clocks 6 Ghz and not a single X86 CPU on TSMC Node clocks that high does that mean all TSMC nodes are bad there is more to a design the length of critical path the pipeline stages the libraries used and many other thing affect clock speed. The only way to compare nodes is to have different companies have the same IP taped out on different node.

 

[Xebec]

I think there are multiple sources on the density aspect of the comparison. There is one Here from Jan 2026 with this quote:

Thanks - and fully agree - I didn't question N2's density advantage - was just curious about the power efficiency.

... but this is TSMC saying it.

Intel does have a track record of making transistors that can clock high though. I do wonder about the hot spot issues discussed in some threads here causing the overall design to need to clock lower because of this, but really that is just my wild speculation.

Another pro for Intel is exactly the fact that 18A is less dense than N2. Generally speaking in engineering "You don't get something for nothing". It is possible that Intel has intentionally given up some density in order to be more power efficient. Rumors are that Zen 6 on N2 will clock to around 6.3-6.4Ghz (with some wild crazy people shouting 7Ghz). I wonder if Intel is aiming at higher clocks, or more power efficiency. I am definitely NOT used to the idea that Intel doesn't have the most transistor density. Spent decades following this technology where Intel lead the entire industry .... sometimes by double the density.

Anyway, the answer for you is that my evidence is pretty slim .

haha, fair -- My personal (silicon outsider) bias is that TSMC's processes tend to be the most efficient.. but at least from public info - 18A is looking pretty strong at efficiency, at least in certain scenarios. and same experience re: transistor density - but it's been almost decade at this point that TSMC has led in density . Apple A12 shipped in Sept 2018 on TSMC N7.

..

18A does have the thermal conductivity handicap of BSPD, so efficiency would be key to keep the total thermal density down. I'm guessing 18A was biased a bit towards efficiency, while 18A-P will be more biased towards performance (as Intel has said the new process improves thermal conductivity by 50% - which allows for more power per transistor).

That said, I feel like efficiency and "max clocks" on process nodes are converging -- to raise max clocks you need to improve efficiency to push voltage curve "up and out". Improving that voltage curve (say going from 1.1V to 1.0V at 5.0 GHz) certainly helps efficiency under load conditions, though idle power may be a different story.

 

[OneEng]

Thanks - and fully agree - I didn't question N2's density advantage - was just curious about the power efficiency.



haha, fair -- My personal (silicon outsider) bias is that TSMC's processes tend to be the most efficient.. but at least from public info - 18A is looking pretty strong at efficiency, at least in certain scenarios. and same experience re: transistor density - but it's been almost decade at this point that TSMC has led in density . Apple A12 shipped in Sept 2018 on TSMC N7.

..

18A does have the thermal conductivity handicap of BSPD, so efficiency would be key to keep the total thermal density down. I'm guessing 18A was biased a bit towards efficiency, while 18A-P will be more biased towards performance (as Intel has said the new process improves thermal conductivity by 50% - which allows for more power per transistor).

That said, I feel like efficiency and "max clocks" on process nodes are converging -- to raise max clocks you need to improve efficiency to push voltage curve "up and out". Improving that voltage curve (say going from 1.1V to 1.0V at 5.0 GHz) certainly helps efficiency under load conditions, though idle power may be a different story.

I think most who follow the technology "feel" like TSMC is likely to produce the more efficient transistors. As you point out, history is now in TSMC's favor.

I do agree that max clocks and efficiency go hand in hand in the most important market (DC) where you are always going to be thermally limited. When you are packing 32+ cores into a single die in the future, getting the heat out becomes a big problem (especially when they may well be stacked). Additionally, I think we are also going to be socket current limited. The socket can only supply so much current. When you pack a monster load of CCD's into a single processor, I suspect that the socket current limit starts to be a big problem.

Where Intel might be very competitive is in low core count, max frequency gaming. 18A and 18A P might be particularly impressive for this use case.

Just when I thought things were settling down, it seems like a whole new angle on scaling (beyond straight forward transistor density improvements) is about to emerge.

Sadly, I think that for consumers, things will definitely slow down as this is very expensive. For DC things are really looking interesting over the next 5 years though.

I have a background in Naval nuclear power. Maybe a pico reactor will be needed in the future to power DC motherboards .

 

[KevinK]

Thought this EMIB yield article for TPUs was also interesting. Based on an X posting by Ming-Chi Kuo, it highlights a few things.
* It highlights both Meta and Google using EMIB for in-house designs (Google TPU 8e)
* EMIB is hitting about 90% yields. I'm not completely sure of the economic impact of packaging yields since they involve a whole lot of pre-tested good die. Could be catastrophic loss of a bunch of good die is EMIB cannot be reworked.
* TSMC’s 5.5-reticle CoWoS platforms are targeting yields starting around 98% in 2026.

[News] Intel’s EMIB Reportedly Gains Traction at Google, Meta; Yields Said to Reach ~90% Milestone

Intel’s leading-edge nodes, spearheaded by 18A, are gradually building momentum, while its advanced packaging portfolio is also showing clear traction...

www.trendforce.com

 

[Xebec]

Thought this EMIB yield article for TPUs was also interesting. Based on an X posting by Ming-Chi Kuo, it highlights a few things.
* It highlights both Meta and Google using EMIB for in-house designs (Google TPU 8e)
* EMIB is hitting about 90% yields. I'm not completely sure of the economic impact of packaging yields since they involve a whole lot of pre-tested good die. Could be catastrophic loss of a bunch of good die is EMIB cannot be reworked.
* TSMC’s 5.5-reticle CoWoS platforms are targeting yields starting around 98% in 2026.

[News] Intel’s EMIB Reportedly Gains Traction at Google, Meta; Yields Said to Reach ~90% Milestone

Intel’s leading-edge nodes, spearheaded by 18A, are gradually building momentum, while its advanced packaging portfolio is also showing clear traction...

www.trendforce.com

The situation with "better packaging" being the way forward with reducing costs and advancing performance reminds me of the complexity problem. If every step in the chain is 99% successful, but there are 50 steps -- you have a high chance of failure even with great engineering.

1. Architecture has to work as designed (errata)
2. Initial product die has to work as designed (< 100% yields)
3. EMIB/CoWoS die sits on has to interconnect and work (< 100% yields)
4. Other dies on the substrates have to work as designed (<100% yields)
5. The substrate has to be defect free (<100% yields)
6. Communications between the dice needs to be reliable (reliability factor)
7. Everything has to work together (<100% yields)
etc..

I think the new packaging techniques are awesome, but I'm wondering what kind of complexity/cost corner the industry is painting itself into.

 

[OneEng]

Clock speed shouldn't be a metric to judge design Intel 7 Raptor Lake clocks 6 Ghz and not a single X86 CPU on TSMC Node clocks that high does that mean all TSMC nodes are bad there is more to a design the length of critical path the pipeline stages the libraries used and many other thing affect clock speed. The only way to compare nodes is to have different companies have the same IP taped out on different node.

Tejas anyone?

While I certainly think that pipeline design effects max clock speed, I also think that today, it's more about the lithography, thermal density, etc, that gives you your max clock.

The situation with "better packaging" being the way forward with reducing costs and advancing performance reminds me of the complexity problem. If every step in the chain is 99% successful, but there are 50 steps -- you have a high chance of failure even with great engineering.

1. Architecture has to work as designed (errata)
2. Initial product die has to work as designed (< 100% yields)
3. EMIB/CoWoS die sits on has to interconnect and work (< 100% yields)
4. Other dies on the substrates have to work as designed (<100% yields)
5. The substrate has to be defect free (<100% yields)
6. Communications between the dice needs to be reliable (reliability factor)
7. Everything has to work together (<100% yields)
etc..

I think the new packaging techniques are awesome, but I'm wondering what kind of complexity/cost corner the industry is painting itself into.

I agree. These super cool (and they really are cool) packaging enhancements really do help keep yields high by the use of smaller individual die (vs monolithic).... but each step can introduce a yield issue.

Years ago, Ford asked me to agree to an acceptance test of the manufacturing test system I was introducing that required >99% first time through rate across 30 test stations, each having ~200 test algorithms and interfacing with external equipment that was different at each station. I can't remember the math now, but it required a pretty insane level of reliability (like <1 PPM) due to the stack up.... and it had to maintain that level without any dip for 2 weeks straight before the team could leave.

It's amazing to me that humans can create tooling that performs at this level. I don't miss dealing (directly) with the manufacturing process at all .

 

[benb]

It is hard to beat the law of "necessity of running large numbers of wafers in Semi-Fab manufacturing". That law seems quite universal, independent of management and geography, valid in Taiwan, USA and Korea.....

This is the fundamental driver of success or failure in foundry--having wafers to run to do the engineering that drives the yields up, drives costs down, and satisfies customers. That's a vicious cycle if you're losing market share, wafers are falling, costs are not falling as fast as the wafer-rich competition, and customers are dissatisfied. Even if it is not stated in public, there's enough evidence of the results--that small market share in Foundry, the contrast of 9 phases (fabs) per year vs. 1 or less.

 

[KevinK]

I think the new packaging techniques are awesome, but I'm wondering what kind of complexity/cost corner the industry is painting itself into.

I agree - just getting all the components correct and tested has a ton of yield attrition. Add in that advanced packaging mistake might render all of those high-value tested-good components worthless. Just saw this timely article that hints at types of possible repairs, though I this article doesn't go into details. (I suspect repair details are in the second installment)

AI Accelerator Testing Depends On DFT Innovations

Multi-die assemblies greatly increase the number of things that can go wrong, and the difficulty of finding them.

semiengineering.com

 

[blueone]

I agree - just getting all the components correct and tested has a ton of yield attrition. Add in that advanced packaging mistake might render all of those high-value tested-good components worthless. Just saw this timely article that hints at types of possible repairs, though I this article doesn't go into details. (I suspect repair details are in the second installment)

AI Accelerator Testing Depends On DFT Innovations

Multi-die assemblies greatly increase the number of things that can go wrong, and the difficulty of finding them.

semiengineering.com

For those of us who worked on multi-node datacenter systems, chiplets and their problems look like a microcosm of the system-level multi-node problems, but with far more technical differentiation, and debugging based on signals rather than message passing. (Yuck.) I've often wondered how chiplet architectures would succeed or fail, or whether common glueware (beyond UCIe) would be developed to make them more practical. Architecting for high performance and low latency also look like problems which require only the best of the best engineers to solve.

 

[OneEng]

This is the fundamental driver of success or failure in foundry--having wafers to run to do the engineering that drives the yields up, drives costs down, and satisfies customers. That's a vicious cycle if you're losing market share, wafers are falling, costs are not falling as fast as the wafer-rich competition, and customers are dissatisfied. Even if it is not stated in public, there's enough evidence of the results--that small market share in Foundry, the contrast of 9 phases (fabs) per year vs. 1 or less.

... and there was a time when the majority of chips being used in the world were used for PC's. In this world, Intel's vertical integration made perfect sense. In today's world where chips are used in a much more varied way across a much wider set of markets, Intel finds itself producing ~2-3M wafers / year to TSMC's >17M wafers / year.

Not sure where all the bean counters and strategists at Intel went, but it doesn't take a rocket scientist to see the problem.

Intel paid over $20Bn to develop 18A. While I am certain TSMC paid something similar for N2 development, They get to spread the cost over 8 times as many wafers.

This is a big problem IMO.