Panther Lake design rules revealed, no HD cells

[Xebec]

I would love to see full technsights report and @Scotten Jones commentary.

So the SRAM cell size is .023. The N2 Cells size from TSMC products shown at ISSCC is what?

I am not sure we will see Nova lake 18A CPU products. Which skus are not N2?

Agreed on 18A Nova Lake; The rumors are unfortunately all over the place, and many don't make sense.

Last September, it was floated that 18A would be for the SoC (I/O, memory controller) tile *or* iGPU -- which seems like a mismatch for 18A, especially given Panther Lake will still be ramping into Q4 2026.

More recent rumors are suggesting 18A-P for some Nova Lake skus, implying perhaps a refresh to boost performance after initial launch. But I don't think 18A-P is going to be ready fast enough for Nova Lake, at least not ~ Dec 2026?

Lastly, the latest rumors are saying Nova Lake will launch at CES 2027, though not completely clear if that's Nova Lake-S or Nova Lake-H. (if even true).

 

[MKWVentures]

Agreed on 18A Nova Lake; The rumors are unfortunately all over the place, and many don't make sense.

Last September, it was floated that 18A would be for the SoC (I/O, memory controller) tile *or* iGPU -- which seems like a mismatch for 18A, especially given Panther Lake will still be ramping into Q4 2026.

More recent rumors are suggesting 18A-P for some Nova Lake skus, implying perhaps a refresh to boost performance after initial launch. But I don't think 18A-P is going to be ready fast enough for Nova Lake, at least not ~ Dec 2026?

Lastly, the latest rumors are saying Nova Lake will launch at CES 2027, though not completely clear if that's Nova Lake-S or Nova Lake-H. (if even true).

Refresh could be anything.

to simplify: On the initial set of SKUs which will launch in 2027 but somehow be claimed to be launched in 2026..... I believe the CPU is all N2. Please correct me if I am wrong.

This is why the term launch is important.... it means there are products I can buy today. Risk production, manufacturing ready, working samples are all ambiguous (There is always a reason to claim these and it doesnt have to do with the health of the technology).

 

[siliconbruh999]

I am not sure we will see Nova lake 18A CPU products. Which skus are not N2?

4+0+4 from the rumors going on while rest of the SKU are N2 also all tiles beside CPU is IFS but the core part is Intel

 

[my_wing]

I would love to see full technsights report and @Scotten Jones commentary.

So the SRAM cell size is .023. The N2 Cells size from TSMC products shown at ISSCC is what?

I am not sure we will see Nova lake 18A CPU products. Which skus are not N2?

I would also love the see the full insight.

The post mentioned that SRAM is Front Side Power i.e. no BSPD, does the SRAM is GAA as well, then the next question is that there is so many TSMC fanboy out there saying Intel can't find an external customer because they don't want to invest into BDSP, but now if the SRAM has no BSPD, how much the difference to have other things e.g. IO or logic to be not BSPD. There are articles that support these TSMC fanboy / AI BOT view point from sources like Toms Hardware that it is difficult for Intel to have an GAA version without BSPD since that is what they invest into. But now if even a single chip / chiplet can mix BSPD and FSPD, that is very very interest, contradict what some like IanD mentioned in other post within this forum.

 

[Xebec]

I would also love the see the full insight.

The post mentioned that SRAM is Front Side Power i.e. no BSPD, does the SRAM is GAA as well, then the next question is that there is so many TSMC fanboy out there saying Intel can't find an external customer because they don't want to invest into BDSP, but now if the SRAM has no BSPD, how much the difference to have other things e.g. IO or logic to be not BSPD. There are articles that support these TSMC fanboy / AI BOT view point from sources like Toms Hardware that it is difficult for Intel to have an GAA version without BSPD since that is what they invest into. But now if even a single chip / chiplet can mix BSPD and FSPD, that is very very interest, contradict what some like IanD mentioned in other post within this forum.

Hi there -- folks like IanD on here are actual professionals working in the field - with a lot more hands on knowledge than anyone you'll see writing articles on the news sites. Intel's challenges with finding customers is not TSMC fanboy-ism - it's unfortunately a market reality. I'm not the full expert, but there are a few reasons I've gathered they've had challenges in getting customers for Intel Foundry are:

1. TSMC is a safe bet - they're delivered consistently for decades as a reliable partner for chip fabrication. A safe bet is usually a good idea when you're spending $B to fabricate chips.

2. Intel's previous PDKs (design kits for determining how to fab an IC on a given node) were not nearly as complete or good as TSMCs. This represents a high engineering (cost) risk for any company considering using Intel to fab their chips*.

3. Intel's internal costs are higher than TSMCs meaning they might not have been offering competitive pricing. (Note this is a partial supposition, but there is data to support the higher costs).

4. Intel Foundry is seen as a potential conflict of interest being both a competitor and foundry partner for potential customers. ex: TSMC doesn't directly compete with Nvidia, AMD, or Apple -- they just provide the services to build chips.

This doesn't mean Intel can't succeed as a Foundry, but the challenges are substantial, indeed.. and this is a very simplified overview - there's a lot more in the 'challenge' and 'threat' departments for Intel. (Though Intel has exceptional engineering talent, and other strengths and opportunities as well).

...

Intel's 18A has BSPD for logic but not for SRAM at Intel's own choice because the technology they hace implemented with BSPD in 18A would *decrease* SRAM density by about 10%. Rumors are this will get addressed in 14A. If you had a really good microscope and a Panther Lake chip - you'd see BSPD wires attached to logic, but not to SRAM. To answer your other question - the SRAM and logic on 18A are both GAAFET (Intel speak: RibbonFET).



*I'm fairly confident an engineer or three here is going to school me on an improper explanation of the PDK here .

 

[my_wing]

Hi there -- folks like IanD on here are actual professionals working in the field - with a lot more hands on knowledge than anyone you'll see writing articles on the news sites. Intel's challenges with finding customers is not TSMC fanboy-ism - it's unfortunately a market reality. I'm not the full expert, but there are a few reasons I've gathered they've had challenges in getting customers for Intel Foundry are:

1. TSMC is a safe bet - they're delivered consistently for decades as a reliable partner for chip fabrication. A safe bet is usually a good idea when you're spending $B to fabricate chips.

2. Intel's previous PDKs (design kits for determining how to fab an IC on a given node) were not nearly as complete or good as TSMCs. This represents a high engineering (cost) risk for any company considering using Intel to fab their chips*.

3. Intel's internal costs are higher than TSMCs meaning they might not have been offering competitive pricing. (Note this is a partial supposition, but there is data to support the higher costs).

4. Intel Foundry is seen as a potential conflict of interest being both a competitor and foundry partner for potential customers. ex: TSMC doesn't directly compete with Nvidia, AMD, or Apple -- they just provide the services to build chips.

This doesn't mean Intel can't succeed as a Foundry, but the challenges are substantial, indeed.. and this is a very simplified overview - there's a lot more in the 'challenge' and 'threat' departments for Intel. (Though Intel has exceptional engineering talent, and other strengths and opportunities as well).

...

Intel's 18A has BSPD for logic but not for SRAM at Intel's own choice because the technology they hace implemented with BSPD in 18A would *decrease* SRAM density by about 10%. Rumors are this will get addressed in 14A. If you had a really good microscope and a Panther Lake chip - you'd see BSPD wires attached to logic, but not to SRAM. To answer your other question - the SRAM and logic on 18A are both GAAFET (Intel speak: RibbonFET).



*I'm fairly confident an engineer or three here is going to school me on an improper explanation of the PDK here .

Maybe my wording is wrongly presented, of course I think IanD is really an expert in the field, therefore I said is interesting, nothing more and nothing less.

I am a finance guy, looking at budget and perform these types of work is my daily task. (Although I took B.Sc and does have Computer Hardware and Circuits), so I understand the complexity and respect knowledge.

But my daily task did not agree with a lot of Wall Street and people alike that Intel has to have foundry customers. That is a nice to have, SK Hynix is a typical pure play semi-conductor manufacturer. The number do work out that Intel can afford to build a modular fab, making the old equipment to be a logistic problem rather then a space problem. The Silicone Disc Pod transport system, instead of adequate buildings is the root cause of problems, i.e. the worst case is that you passing a silicone disc, for KMs around a factory because the old factory can't house a new system that previous not designed for. Instead of optimise floor space, optimise the logistics, in presenting my point, if there is a world that make the transport pod moving in the speed of light, no matter how far the silicone needed to travel, just did not matter. Therefore I don't believe those TSMC PR saying oh building 3nm Japan, 2nm Tainan, 5nm Texas, these are non-sense, same machines, just different quantity, there is no such a thing that a floor plan of 2nm FAB looks like X and 5nm FAB looks like Y, let say a silicone disk need to go through 200 steps in a sequences and can be traveling 100s of KM within the FAB, to me organisation and logistic planning is where AI can shine. Just let AI prepare a schedule for you. No matter how the floor plan is built. No needed to tear down old structure (but if there is really a big bottle neck identified then tear down), that building can run 20-30 years easily, if that is properly support by the Pod system.

Non those write down B/S that Intel put, I would rather look at this a Financial Engineering and book cooking. 90% of all machine ASML "ever" build is still operating, write down in value just Financial Engineering.

With 70%-80% of laptop, 50%-60% of server, if intel can have 10% of GPU as well, including all the IO / Wifi / Chipset la la la that Intel is building, why Intel needed an external customer, that is way more things that Intel is making than SK Hynix and Micron, which is not a foundry. That is why Intel want Tower Semi, the old machine can focus on making mature node.

 

[MKWVentures]

Maybe my wording is wrongly presented, of course I think IanD is really an expert in the field, therefore I said is interesting, nothing more and nothing less.

I am a finance guy, looking at budget and perform these types of work is my daily task. (Although I took B.Sc and does have Computer Hardware and Circuits), so I understand the complexity and respect knowledge.

But my daily task did not agree with a lot of Wall Street and people alike that Intel has to have foundry customers. That is a nice to have, SK Hynix is a typical pure play semi-conductor manufacturer. The number do work out that Intel can afford to build a modular fab, making the old equipment to be a logistic problem rather then a space problem. The Silicone Disc Pod transport system, instead of adequate buildings is the root cause of problems, i.e. the worst case is that you passing a silicone disc, for KMs around a factory because the old factory can't house a new system that previous not designed for. Instead of optimise floor space, optimise the logistics, in presenting my point, if there is a world that make the transport pod moving in the speed of light, no matter how far the silicone needed to travel, just did not matter. Therefore I don't believe those TSMC PR saying oh building 3nmY Japan, 2nm Tainan, 5nm Texas, these are non-sense, same machines, just different quantity, there is no such a thing that a floor plan of 2nm FAB looks like X and 5nm FAB looks like Y, let say a silicone disk need to go through 200 steps in a sequences and can be traveling 100s of KM within the FAB, to me organisation and logistic planning is where AI can shine. Just let AI prepare a schedule for you. No matter how the floor plan is built. No needed to tear down old structure (but if there is really a big bottle neck identified then tear down), that building can run 20-30 years easily, if that is properly support by the Pod system.

Non those write down B/S that Intel put, I would rather look at this a Financial Engineering and book cooking. 90% of all machine ASML "ever" build is still operating, write down in value just Financial Engineering.

With 70%-80% of laptop, 50%-60% of server, if intel can have 10% of GPU as well, including all the IO / Wifi / Chipset la la la that Intel is building, why Intel needed an external customer, that is way more things that Intel is making than SK Hynix and Micron, which is not a foundry. That is why Intel want Tower Semi, the old machine can focus on making mature node.

N2 fabs are different than N5 fabs. they are not necessarily interchangable. I used to tell investors "Picture the most complicated power plant, Most complicated chemical factory/refinery, most complicated assembly line all rolled into one.... thats a Fab."

On the foundry....

Intel does not have the internal volume to support development on advanced nodes. That is why Intel loses money on manufacturing and it got worse not better. In 2020 Intel decided to pursue outsourcing. In 2021 Pat decided to reverse that and do fab AND use foundry to provide the volume to pay for development (its really easy to show how you need volume to pay for leading edge foundry). Foundry customers never came (yet) and so Intel losses pile up.

Intel has less than 1% of the AI GPU market and about 70% of x86 CPU market. This is not enough to pay for development.

So Intel needs to have cost effective processes and external volume to stay in the leading edge fab game. LBT has made this clear as well. The math is pretty simple. This is why successful companies outsource fab manufacturing. custom processes like memory and power/analog are different so those companies must do it internally.

The numbers will tell the story and LBT wont be telling optimistic stories about how the whale is coming real soon and Intel is an unquestioned leader. If the external volume doesnt show up, Intel will correctly stop.

My personal take? Intel will get some foundry interest.... but the financials will be poor. IBM2.0

Lets see what happens.

 

[my_wing]

N2 fabs are different than N5 fabs. they are not necessarily interchangable. I used to tell investors "Picture the most complicated power plant, Most complicated chemical factory/refinery, most complicated assembly line all rolled into one.... thats a Fab."

On the foundry....

Intel does not have the internal volume to support development on advanced nodes. That is why Intel loses money on manufacturing and it got worse not better. In 2020 Intel decided to pursue outsourcing. In 2021 Pat decided to reverse that and do fab AND use foundry to provide the volume to pay for development (its really easy to show how you need volume to pay for leading edge foundry). Foundry customers never came (yet) and so Intel losses pile up.

Intel has less than 1% of the AI GPU market and about 70% of x86 CPU market. This is not enough to pay for development.

So Intel needs to have cost effective processes and external volume to stay in the leading edge fab game. LBT has made this clear as well. The math is pretty simple. This is why successful companies outsource fab manufacturing. custom processes like memory and power/analog are different so those companies must do it internally.

The numbers will tell the story and LBT wont be telling optimistic stories about how the whale is coming real soon and Intel is an unquestioned leader. If the external volume doesnt show up, Intel will correctly stop.

My personal take? Intel will get some foundry interest.... but the financials will be poor. IBM2.0

Lets see what happens.

And SK Hynix only has 21% of NAND, 50% HBM and 36% DRAM does have enough volume. Maths does not add up.

I would like to highlight, Intel under built Intel 3 @ Ireland, 18A @ USA, it is not enough customers (foundry). it is not enough production. Intel alone is AMD, Qualcomm, MediaTek combine, I think before the deal call off, Tower continue to be manufacture in IFS.

There is not such a thing call N3 Vs N2 Fab, if there are, then TSMC can't just said that the initial N4/5 now can like a switch upgrade to N3 (Japan FAB), you don't understand how to run a factory, not I don't understand how to run one, in fact there is a professional call Cost Accountant, which I previously employed for. How I seen is that they needed a Good AI logistic / Cost / Plan system, to track, plan, and forecast how each of the disc is and will be, just like how DHL / TNT / .... track a parcel on the airport.

The problem case needed to be clear, and there is only 1 objective, how to keep a 300 million machine up and running as long as it can, all other machine can dynamically stopped but not the 300 million one.

 

[IanD]

Hi there -- folks like IanD on here are actual professionals working in the field - with a lot more hands on knowledge than anyone you'll see writing articles on the news sites. Intel's challenges with finding customers is not TSMC fanboy-ism - it's unfortunately a market reality. I'm not the full expert, but there are a few reasons I've gathered they've had challenges in getting customers for Intel Foundry are:

1. TSMC is a safe bet - they're delivered consistently for decades as a reliable partner for chip fabrication. A safe bet is usually a good idea when you're spending $B to fabricate chips.

2. Intel's previous PDKs (design kits for determining how to fab an IC on a given node) were not nearly as complete or good as TSMCs. This represents a high engineering (cost) risk for any company considering using Intel to fab their chips*.

3. Intel's internal costs are higher than TSMCs meaning they might not have been offering competitive pricing. (Note this is a partial supposition, but there is data to support the higher costs).

4. Intel Foundry is seen as a potential conflict of interest being both a competitor and foundry partner for potential customers. ex: TSMC doesn't directly compete with Nvidia, AMD, or Apple -- they just provide the services to build chips.

This doesn't mean Intel can't succeed as a Foundry, but the challenges are substantial, indeed.. and this is a very simplified overview - there's a lot more in the 'challenge' and 'threat' departments for Intel. (Though Intel has exceptional engineering talent, and other strengths and opportunities as well).
..

Intel's 18A has BSPD for logic but not for SRAM at Intel's own choice because the technology they hace implemented with BSPD in 18A would *decrease* SRAM density by about 10%. Rumors are this will get addressed in 14A. If you had a really good microscope and a Panther Lake chip - you'd see BSPD wires attached to logic, but not to SRAM. To answer your other question - the SRAM and logic on 18A are both GAAFET (Intel speak: RibbonFET).

*I'm fairly confident an engineer or three here is going to school me on an improper explanation of the PDK here .

By focusing on the raw technology -- all of which I agree with! -- you missed out what is probably at least as important (if not more so) for many ASIC customers, which is the fabled TSMC ecosystem -- a lot of companies providing silicon-proven IP of all varieties in time for your critical design. This IP takes a lot of time and effort and money to develop especially in the latest technologies like N2, and the IP providers develop it in TSMC because they know there will be lots of customers willing to pay for it, because almost everyone uses TSMC.

Now turn it round and ask why they should spend their time and effort developing similar IP for Intel processes, where there are few (or no?) guaranteed customers to pay for it? Even if Intel offers to subsidize their development costs (which I know has been done in the past, and I heard Rapidus are doing...) they're not going to get the same ROI as developing IP for TSMC, so logically that's where they'll put their resources.

I don't have details of Intel's process, but I guess that when they say "no BSPD in SRAM" what they mean is that there are no PowerVias inside the RAM array areas because this decreases density, so here they distribute power through the thinner topside metal layers -- which is OK because RAM doesn't need as many interconnect layers as logic so many will be freed up, and the power density in the array is very low anyway. Whether the power is fed in horizontally from the RAM I/O areas (drive/sense/decode) or using occasional PowerVia columns within the RAM array doesn't matter, the RAM array is effectively FSPD.

 

[siliconbruh999]

I don't have details of Intel's process, but I guess that when they say "no BSPD in SRAM" what they mean is that there are no PowerVias inside the RAM array areas because this decreases density, so here they distribute power through the thinner topside metal layers -- which is OK because RAM doesn't need as many interconnect layers as logic so many will be freed up, and the power density in the array is very low anyway. Whether the power is fed in horizontally from the RAM I/O areas (drive/sense/decode) or using occasional PowerVia columns within the RAM array doesn't matter, the RAM array is effectively FSPD.

I wish you had the PDK i would have liked to hear your opinion on it

 

[IanD]

I wish you had the PDK i would have liked to hear your opinion on it

Even if we were using (or even considering) Intel I wouldn't be allowed to see the PDK, since I have access to the TSMC N2 PDK -- and you have to sign away your life to get this which includes having no involvement with a competitor's process... ;-)

(if a company wants to use both, they need two separate firewalled PD teams...)

 

[swka]

Even if we were using (or even considering) Intel I wouldn't be allowed to see the PDK, since I have access to the TSMC N2 PDK -- and you have to sign away your life to get this which includes having no involvement with a competitor's process... ;-)

(if a company wants to use both, they need two separate firewalled PD teams...)

the kind of policy has been in place, enforced by tsmc for years. imagine any other part of the industry does the same thing. You cannot use Synopsys tools if you have access to cadence ones; you cannot touch Applied equipment if you have Lam machines ... Another behavioral tsmc can have with its dominate market position

 

[swka]

Now turn it round and ask why they should spend their time and effort developing similar IP for Intel processes, where there are few (or no?) guaranteed customers to pay for it? Even if Intel offers to subsidize their development costs (which I know has been done in the past, and I heard Rapidus are doing...) they're not going to get the same ROI as developing IP for TSMC, so logically that's where they'll put their resources.

funny thing is synopsys stocked dropped by 1/3 Oct 2025 most because intel refuse to pay for the IP development fee for 18A (supposedly). not so funny for synopsys share holders

 

[IanD]

the kind of policy has been in place, enforced by tsmc for years. imagine any other part of the industry does the same thing. You cannot use Synopsys tools if you have access to cadence ones; you cannot touch Applied equipment if you have Lam machines ... Another behavioral tsmc can have with its dominate market position

Of course if you don't like this policy you always have a choice -- don't use TSMC... ;-)