Intel’s 18A rumors meet a thermal brick wall says SemiWiki

[siliconbruh999]

The analyst had a copy of Techinsight's analysis so we won't know how true is it cause it's paid.

 

[staf]

IMEC semiconductor roadmap to 2039 assumes BSPD from 2025 on.

Did IMEC not consider the self-heating issue?

You should know that imec in itself is not a company that commercializes chip manufacturing; I've been there in the lithography department. It's a research institute that does research on the building blocks for scaling the microelectronics manufacturing. It would surprise me if they don't have research on new ways of cooling chips.
In the end it is up the IDMs and foundries to put together the building block in a commercial offering or product. It seems in the last 10 years TSMC has been better at this than anyone else.

 

[staf]

And TSMC is already a long time partner in the big imec research programs while Intel has for the longest time thought they could do everything on their own...

 

[Xebec]

And it's all getting gradually worse and worse as processes evolve, because power/current density per mm2 is gradually increasing as more funtionality clocked faster is squeezed into a smaller and smaller area, FinFET had worse SHE than planar, GAA is worse again -- and BSPD throws more fuel onto the fire since this increases both density and clock speeds, as well as having the extra thermal resistance to the heatsink and poorer heat-spreading which makes hotspots worse.

Is there any future possibility of running certain circuits without BSPD and the rest of the chip with BSPD to try to get better cooling in critical spots, or is that not possible due to yields, design rules, etc.?

For example, on 18A -- SRAM cells do not have BSPD because they would actually lose about 10% density. (I've also read claims 14A makes some changes to how BSPD is connected to the transistors that should allow more scaling with BSPD). In the 18A SRAM case, would there be some 'filler' material in place of the PowerVIAs that allows better heat conduction?

 

[IanD]

Is there any future possibility of running certain circuits without BSPD and the rest of the chip with BSPD to try to get better cooling in critical spots, or is that not possible due to yields, design rules, etc.?

For example, on 18A -- SRAM cells do not have BSPD because they would actually lose about 10% density. (I've also read claims 14A makes some changes to how BSPD is connected to the transistors that should allow more scaling with BSPD). In the 18A SRAM case, would there be some 'filler' material in place of the PowerVIAs that allows better heat conduction?

I'd have thought it's pretty much impossible, because the BSPD and FSPD regions have very different metal/substrate topography and the process flow is also different -- also FSPD has the power and I/O bumps on the topside and BSPD has them on the backside. This also makes improved cooling impossible since the chips are the other way up -- FSPD has the substrate at the top (good cooling) with all metal underneath the transistors and then bumps, BSPD has the thin metal/dielectric layers at the top (bad cooling), then the transistors and thin (<1um) substrate, then thick metal and bumps at the bottom. The two are fundamentally incompatible.

Having filler instead of powerVIAs in the SRAM region doesn't help with cooling, it's the wrong side of the chip (bump side not heatsink side). Having said that, SRAM is probably not such a problem for cooling anyway, at least in the memory array area, since power/current density here is very low.

 

[jorgequinonez]

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.

semiengineering.com