Intel’s 18A rumors meet a thermal brick wall says SemiWiki

[Daniel Nenni]

Intel has attracted plenty of chatter over the past few weeks, with talk that Apple could come crawling back for some M-series work, but now it appears that iPhone chips…

Intel has attracted plenty of chatter over the past few weeks, with talk that Apple could come crawling back for some M-series work, but now it appears that iPhone chips on Chipzilla’s fanciest nodes are a non-starter.

In recent weeks, GF Securities and DigiTimes have claimed Apple might use Chipzilla’s 18A-P process for its lowest-end M-series parts in 2027. The same reports floated the possibility of non-Pro iPhone chips in 2028.

GF Securities also said Job’s Mob’s bespoke ASIC, expected in 2028, would use Chipzilla’s EMIB packaging. That is the sort of detail that makes rumours sound “real” while still being completely free of consequences.

There has been noise that Job’s Mob signed an NDA with Intel and pulled PDK samples for 18A-P to evaluate. Chipzilla’s 18A-P is intended to be its first node supporting Foveros Direct 3D hybrid bonding, enabling chiplets stacking via TSVs.

Now, a bunch of industry insiders on the SemiWiki forum have poured cold water on Intel’s manufacturing of iPhone chips. The core gripe is Chipzilla’s decision to go all-in on Backside Power Delivery for its 18A and 14A nodes.

Unlike TSMC, which offers some nodes with BSPD and others without it, Chipzilla has pushed BSPD across its bleeding-edge stack. That leaves it without an easy “same node, less drama” option when a customer prioritises thermals over bragging rights.

BSPD can boost performance because the chip is powered through shorter, thicker metal paths on the backside, cutting voltage drop and helping to stabilise frequencies. It also frees up front-side routing, which can lift transistor density or reduce congestion.

For mobile silicon, insiders reckon the performance bump is small. The trade-off is a worse self-heating effect, which increases cooling requirements in places phones would rather avoid.

SemiWiki forum, commenter IanD said: “kept around 20C cooler with BSPD for the same die temperature in hotspots (because vertical heat spreading is bad but lateral is even worse now there’s no thick silicon substrate), and that’s simply impossible in many use cases which rely on air cooling or have a maximum allowable case temperature.”

X, commentator Jukan said there is “zero chance” that Chipzilla can manufacture Job’s Mob iPhone chips anytime soon, although he thought that M-series parts might still be on the table.

https://fudzilla.com/intels-18a-rumours-meet-a-thermal-brick-wall/

 

[blueone]

If you ever start writing like this, Dan, I'm leaving SemiWiki.

 

[Daniel Nenni]

If you ever start writing like this, Dan, I'm leaving SemiWiki.

I wish they would use AI.........

 

[chipsntexas]

Is there a translator for this rubbish...?

 

[LLL0955]

Just curious, I learned that BSPDN can reduce power consumption compared to FSPDN, so is the heat problem is the truly issue for BSPDN?

 

[hist78]

Intel has attracted plenty of chatter over the past few weeks, with talk that Apple could come crawling back for some M-series work, but now it appears that iPhone chips…

View attachment 4136

Intel has attracted plenty of chatter over the past few weeks, with talk that Apple could come crawling back for some M-series work, but now it appears that iPhone chips on Chipzilla’s fanciest nodes are a non-starter.

In recent weeks, GF Securities and DigiTimes have claimed Apple might use Chipzilla’s 18A-P process for its lowest-end M-series parts in 2027. The same reports floated the possibility of non-Pro iPhone chips in 2028.

GF Securities also said Job’s Mob’s bespoke ASIC, expected in 2028, would use Chipzilla’s EMIB packaging. That is the sort of detail that makes rumours sound “real” while still being completely free of consequences.

There has been noise that Job’s Mob signed an NDA with Intel and pulled PDK samples for 18A-P to evaluate. Chipzilla’s 18A-P is intended to be its first node supporting Foveros Direct 3D hybrid bonding, enabling chiplets stacking via TSVs.

Now, a bunch of industry insiders on the SemiWiki forum have poured cold water on Intel’s manufacturing of iPhone chips. The core gripe is Chipzilla’s decision to go all-in on Backside Power Delivery for its 18A and 14A nodes.

Unlike TSMC, which offers some nodes with BSPD and others without it, Chipzilla has pushed BSPD across its bleeding-edge stack. That leaves it without an easy “same node, less drama” option when a customer prioritises thermals over bragging rights.

BSPD can boost performance because the chip is powered through shorter, thicker metal paths on the backside, cutting voltage drop and helping to stabilise frequencies. It also frees up front-side routing, which can lift transistor density or reduce congestion.

For mobile silicon, insiders reckon the performance bump is small. The trade-off is a worse self-heating effect, which increases cooling requirements in places phones would rather avoid.

SemiWiki forum, commenter IanD said: “kept around 20C cooler with BSPD for the same die temperature in hotspots (because vertical heat spreading is bad but lateral is even worse now there’s no thick silicon substrate), and that’s simply impossible in many use cases which rely on air cooling or have a maximum allowable case temperature.”

X, commentator Jukan said there is “zero chance” that Chipzilla can manufacture Job’s Mob iPhone chips anytime soon, although he thought that M-series parts might still be on the table.

https://fudzilla.com/intels-18a-rumours-meet-a-thermal-brick-wall/

@Daniel Nenni

Congratulations to you and the fellow bloggers. SemiWiki is getting much more attention and mention now.

 

[my_wing]

Just curious, I learned that BSPDN can reduce power consumption compared to FSPDN, so is the heat problem is the truly issue for BSPDN?

No, this is not true.

That rubbish just say when transistor get smaller, there is more heat, just like when you place LED array closer and closer, it will heat up the strip.

1) All transistor FSPD or BSPD going to suffer from this (density vs heat), why only BSPD.
2) Last time I am in high school, Copper (which the signal and power line is make of) is one of the best thermo property out there way better than Silicone, the heat is going to out faster not slower.
3) Last time I am in high school, I learn about the cross cut section thickness the larger the cross cut the lesser the resistance, BSPD will have inherently thicker cable as they separate power and signal into different layers

The only remote places that BSPD is going to be at a disadvantage in heat is:
As better cell utilization rate, packing transistor in a denser manner than FSBD, so accordingly, they said higher density = higher heat but that applies to FSPD too.

 

[IanD]

No, this is not true.

That rubbish just say when transistor get smaller, there is more heat, just like when you place LED array closer and closer, it will heat up the strip.

1) All transistor FSPD or BSPD going to suffer from this (density vs heat), why only BSPD.
2) Last time I am in high school, Copper (which the signal and power line is make of) is one of the best thermo property out there way better than Silicone, the heat is going to out faster not slower.
3) Last time I am in high school, I learn about the cross cut section thickness the larger the cross cut the lesser the resistance, BSPD will have inherently thicker cable as they separate power and signal into different layers

The only remote places that BSPD is going to be at a disadvantage in heat is:
As better cell utilization rate, packing transistor in a denser manner than FSBD, so accordingly, they said higher density = higher heat but that applies to FSPD too.

Speaking as someone who has actually done thermal analysis comparison of FSPD vs. BSPD in real high-performance chips vs. high-school posting about copper thermal conductivity...

In a conventional FSPD chip the die is face down, the transistors are embedded in (or thermally directly connected to) a thick (typically 700um) silicon substrate, which has about half the thermal conductivity of copper. This conducts heat to the back of the die where the heatsink contacts it, as a consequence something like 90% or more of the heat leaves the chip this way. Even with this you get significant hotspots in regions with high power density, either at block level or all the way down to gate level, typically the hottest devices run maybe 20C hotter than the die backside -- the substrate also wicks heat away laterally (heat spreading) which helps keep temperatures down.

There's another path down through all the metal layers to the substrate/PCB but this is much higher thermal resistance because copper coverage on each layer is small, especially through tiny vias in the thin/fine-pitch metal layers, and there's no heatsink/cooler on this side, so only a small amount of heat (less than 10%) leaves this way.

With BSPD the die is flipped the other way up, with BSPD power rails and bumps underneath a very thin die (a few microns at most), with the transistors on top of this and the thin/fine-pitch routing layers on top, with no power rails -- this is where the area saving comes from, plus the supply connections are lower resistance because they go straight from thick metal underneath to the transistors without having to crawl down through the thin metal stack (more than 15 layers).

The problem now is that the thermal connection from the hot transistors up to the topside heatsink is through the thin/fine-pitch metal signal layers, which are *much* higher thermal resistance than silicon -- what copper there is might be 2x the thermal conductivity of silicon but there's not much thermally-contacted coverage of this, the rest is oxide/dielectric which is 100x lower conductivity. As well as this vertical resistance, there's nothing good conducting heat laterally either (unlike a silicon substrate) so small hotspots get even hotter as a result.

The end result is that transistors (e.g. in clock drivers) and circuits with high power density get a *lot* hotter than with FSPD, it's very easy to get an extra 20C (40C total) local temperature rise (actually, you can get even more than this if you don't take special layout precautions). This causes problems with leakage and reliability (electromigration), so especially bad for devices that run all the time 24/365 and need long lifetimes. Things are also made worse if you use the higher density from BSPD to increase gate density, this puts power density (W/mm2) up by another 20% or so (if you have a dense power grid), so you can in theory end up with +50C hotspots (30C worse than FSPD) -- though this may not be so bad in practice since the hottest bits probably don't shrink much.

If you have a chip like this (e.g. in a data center) and you can't allow the circuits to run that hot, the only solution is to keep the top of the die/heatsink cooler than with FSPD, typically by 20C. That will usually mean very aggressive cooling is needed, either with truly massive air-cooled heatsinks or liquid-cooling, and will exclude using BSPD in applications where this isn't possible -- unless you're willing to let the chips get *really* hot sometimes, OK for burst use (throttle down after a few seconds?) or intermittent use or if you don't care whether the chip lasts more than a couple of years...

On top of this the PPD improvement with BSPD depends strongly on the FSPD power grid density -- in high-power chips with a dense power grid (e.g. HPC) the area saving and speed improvement are pretty significant, but in lower-power chips with a less dense power grid (most chips!) these are much smaller. Also the wafer cost is currently considerably higher, by more than the area saving.

All of which is are the underlying reasons behind why TSMC recommends A16 (with BSPD) only for "HPC-type devices -- dense power grid with active cooling". For these BSPD definitely has more pros (including better PPD) than cons, which is why it's being adopted for such devices -- also higher die cost doesn't really matter if the selling price is many thousands of dollars each. Since this (CPUs) is also Intel's main market, going BSPD-only works for them, it's the right choice.

For more "normal" chips -- most of the market by number of chips, and probably also wafer volume in the near future -- FSPD is better than BSPD, and for these TSMC is promoting A14 (for all the right reasons) not A16 (BSPD only) -- and it's why Intel (BSPD-only) don't have much of a chance in this market, they have the wrong process for it. Sure it *could* be used in a mobile and have very good performance, so long as you don't mind the high price and can keep it cool, but that's not usually going to be the case -- or you throttle it down as soon as it gets hot, which certain phones have been heavily criticised for... ;-)

It's worth noting that the hotspot problem with BSPD is likely to get worse in future, because with every new process node the power density per mm2 tends to creep up -- and this will get even worse when stacked CMOS comes along, especially for the "bottom" transistor, which will also increase power density further. Should still be fine for HPC with nice cold liquid cooling (which will however get more challenging...), but even worse for everyone else without such a luxury... :-(

P.S. All the numbers above are examples for high-speed high-power-density circuits -- the actual temperature rises will be smaller for a lot of chips, but the difference will still be there... ;-)
P.P.S. TSMC will do a BSPD version of A14 about a year later, as a next-node follow-on to A16 for the same markets (e.g. HPC)
P.P.P.S. This is also the sensible order, FSPD first to MP to drive down the D0 curve, then BSPD for the reticle-sized HPC chips which really *need* super-low D0...