Kirin 9030: SMIC's first 5 nm class smartphone SoC debuts on Geekbench alongside Huawei Mate 80 Pro Max

[Fred Chen]

Huawei's upcoming Mate 80 Pro Max has shown up on Geekbench with a new Kirin 9030 SoC. It is the first smartphone chip to be manufactured on the SMIC N+3 node.

Anil Ganti, Published 11/25/2025

SMIC had achieved a significant breakthrough in its semiconductor manufacturing prowess. It has successfully fabricated its first-ever 5 nm-grade smartphone SoC via its N+3 process node, which was in development since last year. With a transistor density of roughly 125 Mtr/mm2, it can be compared with Samsung's 5LPE node. The chip in question is the Kirin 9030, and it will power the upcoming Huawei Mate 80 series of smartphones.

It was spotted on Geekbench alongside the Huawei Mate 80 Pro Max (HUAWEI SGT-AL10) with 16 GB of RAM. It has one (likely Taishan) prime CPU core clocked at 2.75 GHz, four cores at 2.27 GHz and four more cores at 1.72 GHz. On top of that, it features a Maleoon 935 GPU, the specs of which are unknown.

The Kirin 9030 scores 1,131 and 4,277 in Geekbench's single and multi-core tests. Weibo leaker Digital Chat Station says this score doesn't reflect its full performance because the chip isn't running at peak speed. Even at full potency, the Kirin 9030 is unlikely to perform anywhere close to the Snapdragon 8 Elite Gen 5 and MediaTek Dimensity, but that is to be expected, given its massive node disadvantage.

Kirin 9030: SMIC's first 5 nm class smartphone SoC debuts on Geekbench alongside Huawei Mate 80 Pro Max

Huawei's upcoming Mate 80 Pro Max has shown up on Geekbench with a new Kirin 9030 SoC. It is the first smartphone chip to be manufactured on the SMIC N+3 node.

www.notebookcheck.net

 

[Fred Chen]

The 125 MTr/mm2 came from a Weibo post on March 24 this year by 定焦数码, later reposted on X the same day by @Jukanlosreve.

If the SMIC N+3 125 MTr/mm2 density is real, then we can project some pitches, using calibration from https://www.angstronomics.com/p/the-truth-of-tsmc-5nm.

If the gate pitch is over 52 nm, then the track metal has gone beyond double patterning; they've crossed a big multipatterning hurdle. If less than 52 nm, then they've found an easier path to 5nm than Samsung or TSMC.

 

[tooLongInEDA]

The 125 MTr/mm2 came from a Weibo post on March 24 this year by 定焦数码, later reposted on X the same day by @Jukanlosreve.

If the SMIC N+3 125 MTr/mm2 density is real, then we can project some pitches, using calibration from https://www.angstronomics.com/p/the-truth-of-tsmc-5nm.

View attachment 3880

If the gate pitch is over 52 nm, then the track metal has gone beyond double patterning; they've crossed a big multipatterning hurdle. If less than 52 nm, then they've found an easier path to 5nm than Samsung or TSMC.

Where's the original source for this 125 MTr/mm2 density claim ? Can't find it amongst the links listed.

 

[Fred Chen]

Where's the original source for this 125 MTr/mm2 density claim ? Can't find it amongst the links listed.

This is the X post I referred to:

https://twitter.com/x/status/1904055677603242410

定焦数码 mentioned it's between TSMC N6 and Samsung 5LPE. 5LPE pitches are given here: https://fuse.wikichip.org/news/2823/samsung-5-nm-and-4-nm-update/. 54 nm gate pitch and 36 nm M2 track pitch, giving 126 MTr/mm2.

 

[LLL0955]

Track minimum number is 4. So M2 could reduce track number to below 6 to relax the pitch (however, this will cause complex metal routine that may lead to extra power consumption).

The main challenge is still to be M0. SMIC N+2 M0 track number is 4 that can not be further reduction. So reduce M0 pitch to below 40nm or reduce M0 power rail CD (N+2 is ~65nm according to Techinsight) are two possible results.

 

[LLL0955]

I predict N+3 may be CPP=54nm

Cell height 220nm ( M0 track pitch 40nm and M0 power rail CD 50nm)

Above will lead density to 124-125 mtr

 

[Fred Chen]

Track minimum number is 4. So M2 could reduce track number to below 6 to relax the pitch (however, this will cause complex metal routine that may lead to extra power consumption).

The main challenge is still to be M0. SMIC N+2 M0 track number is 4 that can not be further reduction. So reduce M0 pitch to below 40nm or reduce M0 power rail CD (N+2 is ~65nm according to Techinsight) are two possible results.

The transistor density uses the standard cell height. For a 6-track cell, it means the cell height is 6 track metal pitches, although the rails occur after every four tracks. The rails would be 3 times the signal track metal width.

I predict N+3 may be CPP=54nm

Cell height 220nm ( M0 track pitch 40nm and M0 power rail CD 50nm)

Above will lead density to 124-125 mtr

If the gate pitch is 54 nm, at 125 MTr/mm2, the cell height would be ~218.4 nm. So if that were 6-track cell height, the minimum track metal pitch would be 36.4 nm. Yes, this pitch can be increased by going to less than 6-track. 5-track would mean the rail would be same as signal width (~43.7 nm pitch).

You can get 220 nm cell height with 5.5 40 nm pitch tracks. The rail would be 40 nm wide while the signal track would be 20 nm wide. With 54 nm gate pitch, it does give 124 MTr/mm2.

Note: I just recalled I posted along these lines a while ago: https://semiwiki.com/forum/threads/smics-5nm-may-be-near.19328/