siliconbruh999
Well-known member
N2 is at least half a quarter away from HVM
TSMC Discloses N2 Defect Density Lower Than N3 At The Same Stage Of Development
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fansink
Well-known member
new data?
As TSMC did not specified, I remember TSMC N3B was reported to be having "serious" issues
TSMC’s 3nm yield rate reportedly just 55% · TechNode
TSMC is struggling with its new 3nm process, with the semiconductor giant's yield rate reportedly far below the standard expected.technode.com
also rumor that Apple was paying only usable die not the whole wafer.
With such a low target, it is not surprise that they can beat it and it is really not mean that much.
That just bring my calculation above making more sense, i.e. N2 is not production ready for a larger chip such as EYPC compute i.e. 50 - 80 mm^2 range, it could be the same 55 - 70% yield if they go ahead. AMD will then only pay for good die not the whole wafer. I also explain why Apple do not jump into N2 right away.
They are not ready !!!!
Apple had a problem with their version of N3 and there was a delay. I believe it was an EUV issue, TSMC reduced the amount of layers to resolve it and better optimize N3. This will not be the case with N2. Several companies have already taped out including Apple and AMD. TSMC does make mistakes but they learn from them. I can assure you Apple does not pay for good die. Stupid rumor.
siliconbruh999
Well-known member
Half a quarter = 1.5 Months and N2 HVM in H2 25 so it's the same date from now use some maths
Half a quarter = 1.5 Months and N2 HVM in H2 25 so it's the same date from now use some maths
From what I hear N2 will be in HVM in Q3 so lets say September 4th, my birthday.
fansink
Well-known member
From what I hear N2 will be in HVM in Q3 so lets say September 4th, my birthday.
Things are now in focus, Ivan the Terrible was born on September 4th, 1530
Things are now in focus, Ivan the Terrible was born on September 4th, 1530
Ivan the Terrible was born August 25, 1530. You are the most fact checked individual on this forum, congrats.
fansink
Well-known member
Ivan the Terrible was born August 25, 1530. You are the most fact checked individual on this forum, congrats.
Oops, asked Grok
siliconbruh999
Well-known member
Happy Birthday in Advance Dan in case I forget to wishFrom what I hear N2 will be in HVM in Q3 so lets say September 4th, my birthday.
September 4th 1530 BC.Things are now in focus, Ivan the Terrible was born on September 4th, 1530
fansink
Well-known member
Ivan the Terrible was born August 25, 1530. You are the most fact checked individual on this forum, congrats.
It was either that or Beyoncé, which IS actually 9/4
TSMC N2 will not ever reach HVM before 2027.From what I hear N2 will be in HVM in Q3 so lets say September 4th, my birthday.
They will just produce a small quantity for AMD EYPC line, this is the fact.
In order to be call HVM in TSMC terms, they need at least one of the following iPhone Apple chip (pro / normal), Intel Laptop / Desktop chip, nVidia GPU / AMD Ryzen.
From the above list:
Apple is planning to skip N2 and move to A16, Intel will use its own 18A (at 70% as previous mentioned by a previous co-CEO), nVidia just released 50XX so not possible, AMD just updated Ryzen, so not possible.
siliconbruh999
Well-known member
Nice one
fansink
Well-known member
Pat, we know it's you, put down the crack pipe, go to confessional, admit your lies, recite 3 "Hail Marys" and 4 "Our Fathers"
MKWVentures
Moderator
way way wrong. I had discussions with TSMC and their customers in December and I can assure you HVM is coming sooner than I originally thought.
When you see the revenue wafer starts on Intel 18A, both internal and external, you will definitely be asking whether this is really HVM in 2026... it might not be in HVM in 2027 depending on your definition of HVM (mine is based on WSPM).
siliconbruh999
Well-known member
Intel's WSPM would entirely based on their demand and their balance sheet not their technical capability even if 18A is HVM ready they need demand to justify the ramping of wafers quickly.
I also forgot Qualcomm rumor to go to Samsung, how many large volume customer remains ???
Pixel Tensor G5 ??
The fact is that there isn't any high volume semi conductor (Xiaomi is using N4P) Amazon ??? (Not High volume), use logic not ears.
You used your ears to think, I used my brain.
You just only can ya-da ya-da ya-da, I am hum ..... hum ... oic
Yes, I remember seeing the same report, a D0 of 1.5 would give 30% yield for a 9 mm x 9 mm chiplet.No my work out is that TSMC N2 D0 above 1
How it works:
What is size of 256 Mb SRAM TSMC Mentioned that the current Yield achieved is 90%+
1) how big is the 256 Mb SRAM
38 Mb/mm^2
SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements
SRAM scales again with GAA transistors.www.tomshardware.com
256 / 38 = ~6.74 i.e. 7mm^2
2) if Intel 18A is use to make such a SRAM chip then
The assume that is a square so I square root that making plus minus 2.7mm * 2.7mm and using the D0 to yield calculator
Enter Intel 18A presented D0 figure i.e. 0.4 and if that is true that is 97% yield
Die Yield Calculator - iSine
DIE YIELD CALCULATOR Use this online calculator to figure out die yield using Murphy’s model. You’ll need to know the die size, wafer diameter, and defect density. iSine is your complete resource for ASIC design – from concept to manufacturing and testing. We have expertise in system...isine.com
3) how High the number (high is worse) that D0 to go before it dip to around 90% yield as TSMC mentioned.
The answer is D0 > 1.0 && D0 < 1.5
I am not sure myself but if the calculation is right, please TSMC don't DREAM that they can produce EYPC, that at least needed to be below D0 < 1.0 now for 6 month improvement to D0 < 0.4 this just sound too far fetch for TSMC.
Sorry TSMC is way behind Intel 18A if such a small SRAM currently can only be D0 < 1.5
But this is for an SRAM macro. It might be different for other chips: https://www.digitimes.com/news/a20250325PD228/tsmc-2nm-fab-yield-rate-2025.html
Just watched this video
Around the minute 8. According to Ben the presenter, their "best wafer" yield is typically a good leading indicator of "median wafer" yield in the upcoming quarters. And their current "best wafer" yield already exceeded HVM median wafer yield target (presumablly somewhere around 0.1-0.15 D0).
Furthermore, the same guy said, overall this 18A yield is equal or better than the yield Intel had for all the leading edge processes in the last 15 years, even including 22nm.