3D DRAM era begins: SK Hynix 5-layer demo with hybrid wafer bonding at VLSI 2024

[Fred Chen]

Symposium on VLSI Technology and Circuits

vlsi24.mapyourshow.com

Joodong Park1, kangsik Choi1, Seunghwan Kim1, Jungwon Seo1, Hongseong Kang1, Seungwan Chu1, Seokwon Bae1, Jeonghoon Kwon1, Gilseop Kim1, Yongtaek Park1, Junha Kwak1, Dongil Song1, Sungmean Park1, Yongtaik Kim1, Kyoungchul Jang1, Jinsun Cho1, Heesun Lee1, Byungho Lee1, Jinwon Park1, Jihye Lee1, Hyuk Kwon1, Dosun You1, Chansun Hyun1, Jaejung Lee1, Seungcheol Lee1, Ildo Kim1, Juhyun Myung1, Hyungsik Won1, Junho Cheon1, Kyunghoon Kim1, Jiho Kang1, Seungbum Kim1, Kihong Lee1, Suock Chung1, Seonsoon Kim1, Byoungki Lee1, Choonhwan Kim1, Seonyong Cha1 1SKhynix

Three dimensional structured DRAM technology has drawn huge attention recently for its potential to fulfill high speed operation and low power consumption. In this paper, 3D DRAM with vertical bit line (BL) architecture is introduced as a promising solution to overcome scaling limitation for future DRAM technology. Full chip integration with 5-layered cell stacked on peri-core wafer is successfully demonstrated for the first time, offering superior on-current performance and gate controllability. A novel process integration scheme using Si/SiGe sacrificial multilayers and hybrid wafer bonding technique is presented with excellent full chip operation of 3D DRAM.

 

[nghanayem]

Do you know what the gap between VLSI and the papers getting uploaded to IEEE Xplore tends to be for those of us who couldn't attend VLSI?

 

[Paul2]

Symposium on VLSI Technology and Circuits

vlsi24.mapyourshow.com

Joodong Park1, kangsik Choi1, Seunghwan Kim1, Jungwon Seo1, Hongseong Kang1, Seungwan Chu1, Seokwon Bae1, Jeonghoon Kwon1, Gilseop Kim1, Yongtaek Park1, Junha Kwak1, Dongil Song1, Sungmean Park1, Yongtaik Kim1, Kyoungchul Jang1, Jinsun Cho1, Heesun Lee1, Byungho Lee1, Jinwon Park1, Jihye Lee1, Hyuk Kwon1, Dosun You1, Chansun Hyun1, Jaejung Lee1, Seungcheol Lee1, Ildo Kim1, Juhyun Myung1, Hyungsik Won1, Junho Cheon1, Kyunghoon Kim1, Jiho Kang1, Seungbum Kim1, Kihong Lee1, Suock Chung1, Seonsoon Kim1, Byoungki Lee1, Choonhwan Kim1, Seonyong Cha1 1SKhynix

Three dimensional structured DRAM technology has drawn huge attention recently for its potential to fulfill high speed operation and low power consumption. In this paper, 3D DRAM with vertical bit line (BL) architecture is introduced as a promising solution to overcome scaling limitation for future DRAM technology. Full chip integration with 5-layered cell stacked on peri-core wafer is successfully demonstrated for the first time, offering superior on-current performance and gate controllability. A novel process integration scheme using Si/SiGe sacrificial multilayers and hybrid wafer bonding technique is presented with excellent full chip operation of 3D DRAM.

This is not a monolithic-3D DRAM, so the area rule economics will not change.

The real monolithic 3D DRAM promise dramatic per-cm² and per-bit cost reduction, this only allows to squeeze more DRAM dies into a single package.

 

[nghanayem]

This is not a monolithic-3D DRAM, so the area rule economics will not change.

The real monolithic 3D DRAM promise dramatic per-cm² and per-bit cost reduction, this only allows to squeeze more DRAM dies into a single package.

It is monolithic. The only thing being bonded is the periphery logic which is already formed separately from the array (just on the same wafer). The application of hybrid bonding SK described is similar to YMTC's and Kioxia's most recent implementations of CMOS under array 3D-NAND.

Image credit from a similar Samsung paper:

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10185290

 

[Paul2]

It is monolithic. The only thing being bonded is the periphery logic which is already formed separately from the array (just on the same wafer). The application of hybrid bonding SK described is similar to YMTC's and Kioxia's most recent implementations of CMOS under array 3D-NAND.

Image credit:

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10185290

View attachment 2158

My bad, I got distracted by mentions of wafer bonding

 

[MKWVentures]

I have heard that there is no final design yet and that everything is still options and experiments. After they finalize design, it would be 4-5 years to get first product out to sell. Is this still true

 

[nghanayem]

I have heard that there is no final design yet and that everything is still options and experiments. After they finalize design, it would be 4-5 years to get first product out to sell. Is this still true

Seems like process definition from the big three is soon. Especially if we do end up seeing 3D sometime in the early 2030s. Micron also seems to be more silent about 3D than Samsung or SK. So they are either executing on an existing definition (as once you get to that point semi firms tend to go radio silent on any progress), or they are very far behind on 3D dram like IMF was with the jump to 3D NAND.

 

[Fred Chen]

Do you know what the gap between VLSI and the papers getting uploaded to IEEE Xplore tends to be for those of us who couldn't attend VLSI?

It should be less than 3 months.

 

[Fred Chen]

I have heard that there is no final design yet and that everything is still options and experiments. After they finalize design, it would be 4-5 years to get first product out to sell. Is this still true

That would make sense. This is the first demo with bonded periphery/core.