Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

[Daniel Nenni]

Method of metal integration for fabricating integrated device​

Abstract​

The fabrication of integrated devices, for example, integrated semiconductor devices is disclosed. The method for metal integration can be used in a process flow for fabricating such an integrated device. The method is based on patterning different spacers and defining different metal structures using the spacers in two separated steps. In particular, metal structures of a first metal material (61) are processed in a different step than metal structure of a second metal material (91).

Images (49)​

Description
A METHOD OF METAL INTEGRATION FOR FABRICATING AN INTEGRATED DEVICETECHNICAL FIELD
The present disclosure relates to the fabrication of integrated devices, for example, of integrated semiconductor devices. The disclosure presents a method for metal integration, which can be used in a process flow for fabricating such an integrated device.

WO2023236103A1 - Method of metal integration for fabricating integrated device - Google Patents

The fabrication of integrated devices, for example, integrated semiconductor devices is disclosed. The method for metal integration can be used in a process flow for fabricating such an integrated device. The method is based on patterning different spacers and defining different metal structures...

patents.google.com

 

[Daniel Nenni]

As I mention before, where there is a will there is a way, put someone's semiconductor back against the wall, etc... Design complexity and yield are another issue but this looks promising.

SMIC and Huawei might use quadruple patterning for China-designed 5nm chips: Report - Tech Gate

Something that almost killed Intel is now patented in China. But it remains to be seen how viable it will be.

tech-gate.org

 

[soAsian]

As I mention before, where there is a will there is a way, put someone's semiconductor back against the wall, etc... Design complexity and yield are another issue but this looks promising.

SMIC and Huawei might use quadruple patterning for China-designed 5nm chips: Report - Tech Gate

Something that almost killed Intel is now patented in China. But it remains to be seen how viable it will be.

tech-gate.org

The US's actions so far seem designed to slow down China.

 

[Mooredaddy]

I guess it works but it seems like an exceedingly inefficient and uneconomical way of going about things. Hard to believe they could ever turn a profit that way but I guess the CCP will bankroll them

 

[milesgehm]

I hope this is the fault of AI translation and not an indicator of the author’s intelligence “These days it’s principally based totally on want from within the area and in a roundabout way patrons in China want to possess aggressive merchandise and options, this kind of as an Iphone from Apple. That is the place Huawei might nicely use the tech, for buyer process-on-chip design and magnificence, however its chipmaking husband or spouse SMIC has to seize up and this lastly consists of achieving refined chipmaking process applied sciences”

 

[Fred Chen]

I guess it works but it seems like an exceedingly inefficient and uneconomical way of going about things. Hard to believe they could ever turn a profit that way but I guess the CCP will bankroll them

Huawei Tests Brute-Force Method for Making More Advanced Chips

Huawei Tests Brute-Force Method for Making More Advanced Chips (Bloomberg) -- Huawei Technologies Co. and a secretive chipmaking partner in China have filed patents for a low-tech but potentially effective way to make advanced semiconductors, raising the prospect that China could improve chip...

semiwiki.com

Details of this patent was just disclosed in the paper titled "Mandrel/spacer engineering based patterning and metallization incorporating metal layer division and rigorously self-aligned vias & cuts (SAVC)” in 2024 SPIE Advanced Lithography + Patterning, and their amazing effort will be soon seen in Proc. of SPIE in May.

 

[milesgehm]

Details of this patent was just disclosed in the paper titled "Mandrel/spacer engineering based patterning and metallization incorporating metal layer division and rigorously self-aligned vias & cuts (SAVC)” in 2024 SPIE Advanced Lithography + Patterning, and their amazing effort will be soon seen in Proc. of SPIE in May.

This was the first paper on Tuesday morning at SPIE after the plenary session. The authors are all from Westlake University (China). I'm surprised it didn't get more attention at the time. Do they have experimental results? The lead author made this linkedin post a couple of months ago...

Yijian Chen on LinkedIn: Do we need a high-NA EUV scanner to scale down to14A logic node…

Do we need a high-NA EUV scanner to scale down to14A logic node (assumingly with a minimum metal pitch of about 12nm)? Probably 193i DUV lithography can still…

www.linkedin.com

 

[chenyj]

It is still on the early stage of process development. This paper reported some preliminary experimental results of a simplified grating structure using Ru (& direct metal etch), not a fully integrated detailed result, but good enough to show the potential of this technology, including a vertically staggered metal structure to reduce the metal coupling capacitance.

 

[chenyj]

It looks a lot of social news such as 知乎 about Huawei patents in Chinese local-net have been blocked (404, only a few produced by bigger media guys left). What do you think? This cannot be achieved by a simply private company, it's backed by party/government and the whole country's effort! It looks they have very conflicting attitude: on one hand, they hope Chinese people are encouraged by the fake patent news and keep supporting the party; on the other hand, they are afraid of the technical truth disclosed by many real experts.

 

[Barnsley]

https://www.tomshardware.com/tech-i...m-chips-reportshare&utm_medium=member_android

Down to 4 already!

 

[chenyj]

The provided link doesn’t seem to work. It’s unclear what was posted in Tom’s Hardware. You mean 4nm? or what else?

 

[Fred Chen]

The original source of report is Bloomberg, quoted here: https://finance.yahoo.com/news/huawei-tests-brute-force-method-103454340.html

The referred Huawei's patent application was said to be released 3/22/2024 in CNIPA system, which requires login to read. It might take a while to show up in Google Patents.

The other referred SAQP patent is from SiCarrier (Shenzhen Xinkailai) which a patent search will show it to be CN117080054 https://patents.google.com/patent/CN117080054A/en?q=SAQP&assignee=Shenzhen+Xinkailai+

 

[Barnsley]

The provided link doesn’t seem to work. It’s unclear what was posted in Tom’s Hardware. You mean 4nm? or what else?

Wow!

Taken down already!!

The article said that the Chinese were focusing on quad patterning.

I was on phone so couldnt copy paste

 

[KevinK]

The real question in my mind is what is the yield outcome and costs of all the extra steps ? If the eventual cost continues to be a 40-50% premium over comparable TSMC costs, what does that mean for end products using advanced processes ?

SMIC to Mass Produce 5nm Chips for Huawei, Costly and Low Efficiency

Semiconductor Manufacturing International Corp (SMIC), China’s largest chip maker, is planning to mass-produce 5-nanometer chips for Huawei Technologies later this year, despite facing low yields and high production costs. This decision is seen as a strategic move by Huawei and SMIC to...

abachy.com

 

[tonyget]

The real question in my mind is what is the yield outcome and costs of all the extra steps ? If the eventual cost continues to be a 40-50% premium over comparable TSMC costs, what does that mean for end products using advanced processes ?

SMIC to Mass Produce 5nm Chips for Huawei, Costly and Low Efficiency

Semiconductor Manufacturing International Corp (SMIC), China’s largest chip maker, is planning to mass-produce 5-nanometer chips for Huawei Technologies later this year, despite facing low yields and high production costs. This decision is seen as a strategic move by Huawei and SMIC to...

abachy.com

Judging from this graph，DUV SAQP is around 30% more expensive than EUV single pattern. But fabs in China has lower operational costs than Taiwan in general，so SMIC 7/5nm might not be that expensive compare to TSMC Taiwanese fabs，let alone TSMC US fab（probably the most expensive fab for the same node process in the world）.

 

[KevinK]

DUV SAQP is around 30% more expensive than EUV single pattern.

That‘s just the patterning cost of extra steps. What about the yield hit ? Pretty sure that’s not factored in, and of course highly depends on die size as well as type of design and where the foundry is in the yield curve. I’m pretty sure that’s the place where TSMC excels, based on scale and first mover advantages.

 

[Paul2]

I guess it works but it seems like an exceedingly inefficient and uneconomical way of going about things. Hard to believe they could ever turn a profit that way but I guess the CCP will bankroll them

Much of bottom lines of state companies in China conceals stealth subsidies. Double digit of them.

So just more of companies getting kept alive with direct cash disbursement will not be anything unusual, but China's non-subsidised private sector economy slowing down means less cash for state companies, and at some point the breakage of complex supply chains kept alive by subsidy may snowball.

Running a double digit of the industry on subsidy, and the most complex part of it, is a recipe for a very fragile economy.

 

[tonyget]

That‘s just the patterning cost of extra steps. What about the yield hit ? Pretty sure that’s not factored in, and of course highly depends on die size as well as type of design and where the foundry is in the yield curve. I’m pretty sure that’s the place where TSMC excels, based on scale and first mover advantages.

Yield is never constant for any fab, it improves overtime.

 

[tonyget]

Much of bottom lines of state companies in China conceals stealth subsidies. Double digit of them.

So just more of companies getting kept alive with direct cash disbursement will not be anything unusual, but China's non-subsidised private sector economy slowing down means less cash for state companies, and at some point the breakage of complex supply chains kept alive by subsidy may snowball.

Running a double digit of the industry on subsidy, and the most complex part of it, is a recipe for a very fragile economy.

Unfortunately everybody is dragged into this semiconductor subsidy race now，with government all over the global giving out more and more subsidy as we speak.

 

[KevinK]

Yield is never constant for any fab, it improves overtime.

That‘s true, but if your yield for 5nm is 50% when the other guy’s is 90% for the same kind of chip, that’s a formula for losing money. And the yield learning curve is a function of scale and number of varied designs, etc. So SMIC / Huawei is never going to be ahead of foundries with higher volumes at comparable nodes, just far higher costs.