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18A claims from Semiwiki's favorite dart thrower
- Thread starter nghanayem
- Start date
MKWVentures
Moderator
If anything, with backside power delivery and CFET, they would take the opportunity to relax the metal pitches.
I believe Intel commented on this during one the discussions after the presentations at IEDM. M0 has more room with BSP at least with CFET
Does someone have info that Dylan's comment is not correct (TiN/W) for M0?