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The problem with counting fins is that we do not really know the strength/drive of the fins, and just using the cell height without incorporating the poly pitch is also misleading.
Hmm...quite surprised to see Samsung cell height here. The graph doesn't show us how capable each fin is, but at least they 'can' make small fins(apart from various schemes like SDB, COAG...etc). Maybe that's one of the reasons why parametric yields were horrible.
The problem with counting fins is that we do not really know the strength/drive of the fins, and just using the cell height without incorporating the poly pitch is also misleading.
We waited for this. Here is Samsung's true 4nm, 4LPE. We saw Qualcomm Snapdragon 8 gen1 has 4LPX and hardly found “4nm” features. Then, our next interst...
The actual article is not that great and their point is frankly wrong. Intel published at IEDM'18 the three cell heights and fin counts for their 10nm process (now Intel 7) and it is clear they are 5/4 and 4/3 not 4/4, 3/3 in terms of fin counts, so their graph needs to be corrected if they want to be pedantic on the HD library.
Also making the claim that you can't compare scaling from the HP 5/4 lib on Intel 7 to the HP 3/3 lib on Intel 4 because "less fins" is laughable. This is the entire industry direction with "DTCO", in that you want to increase drive per fin while reducing device cap through depopulation. Why are they not arguing TSMC "can't compare their N7 2/2 HD to the 4/4 HD on N16"? The HP library and HD library are whatever is offered on the process technology, and comparing scaling from HP on one node to HP on another is completely legitimate.
How does this author expect to compare fins to GAA when they are setting this orthodoxy?
The actual article is not that great and their point is frankly wrong. Intel published at IEDM'18 the three cell heights and fin counts for their 10nm process (now Intel 7) and it is clear they are 5/4 and 4/3 not 4/4, 3/3 in terms of fin counts, so their graph needs to be corrected if they want to be pedantic on the HD library.
Also making the claim that you can't compare scaling from the HP 5/4 lib on Intel 7 to the HP 3/3 lib on Intel 4 because "less fins" is laughable. This is the entire industry direction with "DTCO", in that you want to increase drive per fin while reducing device cap through depopulation. Why are they not arguing TSMC "can't compare their N7 2/2 HD to the 4/4 HD on N16"? The HP library and HD library are whatever is offered on the process technology, and comparing scaling from HP on one node to HP on another is completely legitimate.
How does this author expect to compare fins to GAA when they are setting this orthodoxy?
Intel 7's 4/4 was just mentioned in their VLSI paper this year, it's just one of the cases. Fin depopulation should be expected, so the lines across more nodes should not be stacked on top of one another but more staggered.
