Samsung demonstrates 3GAE Gate-All-Around MBCFETs at ISSCC 2021

[Fred Chen]

Samsung Demos 256Mb 3nm MBCFET Chip: Performance, Density Up, Power Down

Samsung describes MBCFET-based SRAM.

www.tomshardware.com

"In general, Samsung says that when compared to its 7LPP technology, its 3GAE node will enable an up to 30% performance improvement (at the same power and complexity), up to 50% lower power (at the same clocks and complexity), and an up to 80% higher transistor density (which includes a mix of logic and SRAM transistors)."

 

[Paul2]

Samsung Demos 256Mb 3nm MBCFET Chip: Performance, Density Up, Power Down

Samsung describes MBCFET-based SRAM.

www.tomshardware.com

"In general, Samsung says that when compared to its 7LPP technology, its 3GAE node will enable an up to 30% performance improvement (at the same power and complexity), up to 50% lower power (at the same clocks and complexity), and an up to 80% higher transistor density (which includes a mix of logic and SRAM transistors)."

SRAM needs an underline here.

 

[Daniel Nenni]

What are the density numbers? How does that compare to TSMC 3nm? Or TSMC 5nm?

By the way, the article referenced is gleamed from this source:

Samsung’s 3-nm Tech Shows Nanosheet Transistor Advantage - Spectrum IEEE

 

[Fred Chen]

If the 56 mm2 is the size of the 256 Mb SRAM, that's a really large cell size.

 

[Daniel Nenni]

Scott Jones did a comparison here:

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era - Semiwiki

I was asked to give a talk at the 2021 ISS conference and the following is a write up of the talk. The title of the talk is “Logic Leadership in the PPAC era”. The talk is broken up into three main sections: Background information explaining PPAC and Standard Cells. A node-by-node comparisons of...

semiwiki.com

Spoiler alert: Samsung is behind TSMC in density @ 3nm (FinFET vs GAE).

 

[Fred Chen]

It's strange they didn't use this opportunity to give SRAM cell size, only die size.

 

[Paul2]

Scott Jones did a comparison here:

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era - Semiwiki

I was asked to give a talk at the 2021 ISS conference and the following is a write up of the talk. The title of the talk is “Logic Leadership in the PPAC era”. The talk is broken up into three main sections: Background information explaining PPAC and Standard Cells. A node-by-node comparisons of...

semiwiki.com

Spoiler alert: Samsung is behind TSMC in density @ 3nm (FinFET vs GAE).

Not like just behind, but severely, 1.5 generations behind.

 

[Fred Chen]

Well nanosheets are like fins lying on their side, so the horizontal width would not be as small as expected from the fin pitch anymore. I wonder if this causes some reverse scaling. Surely, for single fin locations.