TSMC targets for 7nm and 10nm

[Fred Chen]

This was some time ago, but it seems to indicate TSMC had extremely aggressive targets for 10nm and 7nm nodes, much more aggressive than Samsung or IMEC, quite close to Intel even.

Cliff Hou, TSMC VP R and D, on the route to 10nm - and beyond

40 nm pitch for '10nm' and 30 nm pitch for '7nm'. Did they really achieve?

"In lithography, Hou said TSMC would push immersion approaches as far as possible, using spacer technology to deliver 40nm metal pitches for 10nm, and double spacer technology to achieve 30nm pitch for 7nm. TSMC is also considering directed self-assembly as an option at 16 nm half pitch."

 

[Daniel Nenni]

This was some time ago, but it seems to indicate TSMC had extremely aggressive targets for 10nm and 7nm nodes, much more aggressive than Samsung or IMEC, quite close to Intel even.

Cliff Hou, TSMC VP R and D, on the route to 10nm - and beyond

40 nm pitch for '10nm' and 30 nm pitch for '7nm'. Did they really achieve?

"In lithography, Hou said TSMC would push immersion approaches as far as possible, using spacer technology to deliver 40nm metal pitches for 10nm, and double spacer technology to achieve 30nm pitch for 7nm. TSMC is also considering directed self-assembly as an option at 16 nm half pitch."

Maybe this information will be discussed at SEMICON West next week, I will let you know. Thus far however it has only been disclosed under strict NDA.

 

[Scotten Jones]

This was some time ago, but it seems to indicate TSMC had extremely aggressive targets for 10nm and 7nm nodes, much more aggressive than Samsung or IMEC, quite close to Intel even.

Cliff Hou, TSMC VP R and D, on the route to 10nm - and beyond

40 nm pitch for '10nm' and 30 nm pitch for '7nm'. Did they really achieve?

"In lithography, Hou said TSMC would push immersion approaches as far as possible, using spacer technology to deliver 40nm metal pitches for 10nm, and double spacer technology to achieve 30nm pitch for 7nm. TSMC is also considering directed self-assembly as an option at 16 nm half pitch."

The pitches I have seen for TSMC at 10nm are 4x nm for MMP and 6x nm for CPP which makes 10nm more of a 12nm half node. TSMC's 7nm pitches are also I believe more like a true 10nm process with high 3x nm MMP and 5x nm CPP. I will be covering this is my talk at SEMICON next week.

 

[Fred Chen]

The pitches I have seen for TSMC at 10nm are 4x nm for MMP and 6x nm for CPP which makes 10nm more of a 12nm half node. TSMC's 7nm pitches are also I believe more like a true 10nm process with high 3x nm MMP and 5x nm CPP. I will be covering this is my talk at SEMICON next week.

Scotten thanks; in the end tightest pitch is what matters not node name.