Morgan Stanley reports Intel 18A yield at 50%

[Fred Chen]

Technology analyst Jukan pointed out on social media that, according to a report issued by Morgan Stanley, Intel's 18A process (compared to TSMC's 2nm) has a yield rate of only 50%, and the company is currently working hard to improve its yield level. The report indicates that customers have a high level of interest in Intel's foundry services, but progress in actually winning customers remains limited.

In contrast, demand for Intel's advanced packaging EMIB is extremely strong, primarily from MediaTek, Trainium (AWS's custom ASIC), and other customers looking for alternatives to TSMC.

傻眼了！摩根士丹利揭英特爾18A良率只有「這麼多」 - 自由財經

〔財經頻道／綜合報導〕科技分析師Jukan在社群平台上指出，根據摩根士丹利出具的報告，英特爾18A製程（對標台積電2奈米）良率僅50%，目前正持續努力提升良率水準，報告指，客戶對英特爾代工服務的

ec.ltn.com.tw

 

[siliconbruh999]

Technology analyst Jukan pointed out on social media that, according to a report issued by Morgan Stanley, Intel's 18A process (compared to TSMC's 2nm) has a yield rate of only 50%, and the company is currently working hard to improve its yield level. The report indicates that customers have a high level of interest in Intel's foundry services, but progress in actually winning customers remains limited.

In contrast, demand for Intel's advanced packaging EMIB is extremely strong, primarily from MediaTek, Trainium (AWS's custom ASIC), and other customers looking for alternatives to TSMC.

傻眼了！摩根士丹利揭英特爾18A良率只有「這麼多」 - 自由財經

〔財經頻道／綜合報導〕科技分析師Jukan在社群平台上指出，根據摩根士丹利出具的報告，英特爾18A製程（對標台積電2奈米）良率僅50%，目前正持續努力提升良率水準，報告指，客戶對英特爾代工服務的

ec.ltn.com.tw

someone posted this on twitter below the tweet

 

[NY_Sam2]

could be wrong, just an educated guess, Intel 18A, 3x2 or 3x5 dies per field?

 

[Fred Chen]

someone posted this on twitter below the tweet
View attachment 4674

It was the same with the 7%/month. Probably safest to assume yield dominated by Panther Lake (~114 mm2).

 

[Xebec]

Is the source Reuters?

 

[Fred Chen]

Interesting comment from CFO here at Morgan Stanley conference back in March: https://ca.investing.com/news/trans...-strategic-shifts-and-challenges-93CH-4495199

"As you might imagine, you know, when you’re, when you’re trying to like lock yields down and get on a kind of a steady path, you somewhat give up on the throughput a little bit to make sure that you’re delivering yield. Our days per mask layer, kind of how we measure it, you know, has kind of eked up a little bit, just to get the yields to start to follow along the right progression. Now that we’re there, I think looking at days per mask layer and trying to shrink that, I think makes a lot of sense."

 

[siliconbruh999]

It was the same with the 7%/month. Probably safest to assume yield dominated by Panther Lake (~114 mm2).

There was one news of 65% Yield as well

 

[MKWVentures]

It was the same with the 7%/month. Probably safest to assume yield dominated by Panther Lake (~114 mm2).

As I mentioned before, to my surprise, the yield did increase 7% per month over the last year (1.07x mor3 DPW each month). The yield intel tracks is Panther lake CPU at wafer sort. There are still packaged unit losses after that and binning

I dont recommend try to get too into arguing the details on TSMC vs Intel Yield due to the complexity of test flow and die sizes. The key is final cost on the products and Intel has line of sight to breakeven on the product.

Intel is very aware of the differences in yield between N2 and 18A since they make products on both processes.

 

[Daniel Nenni]

As I mentioned before, to my surprise, the yield did increase 7% per month over the last year (1.07x mor3 DPW each month). The yield intel tracks is Panther lake CPU at wafer sort. There are still packaged unit losses after that and binning

I dont recommend try to get too into arguing the details on TSMC vs Intel Yield due to the complexity of test flow and die sizes. The key is final cost on the products and Intel has line of sight to breakeven on the product.

Intel is very aware of the differences in yield between N2 and 18A since they make products on both processes.

A big difference this time around is that Lip-Bu Tan brought in PDF Solutions to help with yield. They are experts and outside eyes looking in is a valuable input for Intel. From what I have heard Lip-Bu has regular calls with the founder and CEO of PDF John Kibarian. I can assure you Lip-BU will be a yield expert if he isn't already. The hardest thing to do is ask for help. This has been a major Intel cultural problem that has been addressed, absolutely.

 

[hist78]

As I mentioned before, to my surprise, the yield did increase 7% per month over the last year (1.07x mor3 DPW each month). The yield intel tracks is Panther lake CPU at wafer sort. There are still packaged unit losses after that and binning

I dont recommend try to get too into arguing the details on TSMC vs Intel Yield due to the complexity of test flow and die sizes. The key is final cost on the products and Intel has line of sight to breakeven on the product.

Intel is very aware of the differences in yield between N2 and 18A since they make products on both processes.

I am not sure how this 7% monthly yield improvement on 18A was calculated. However, 12 months after May 2025, shouldn't Intel 18A yield have reached at least 70%–80%, if not higher, regardless of how this 7% monthly improvement is measured?

 

[Daniel Nenni]

In contrast, demand for Intel's advanced packaging EMIB is extremely strong, primarily from MediaTek, Trainium (AWS's custom ASIC), and other customers looking for alternatives to TSMC.

傻眼了！摩根士丹利揭英特爾18A良率只有「這麼多」 - 自由財經

〔財經頻道／綜合報導〕科技分析師Jukan在社群平台上指出，根據摩根士丹利出具的報告，英特爾18A製程（對標台積電2奈米）良率僅50%，目前正持續努力提升良率水準，報告指，客戶對英特爾代工服務的

ec.ltn.com.tw

The NOT TSMC Market is growing. Remember, TSMC does not package other foundry dies so if the design isn't 100% TSMC packaging goes elsewhere, so this is not just a packaging capacity constraint.

 

[siliconbruh999]

I am not sure how this 7% monthly yield improvement on 18A was calculated. However, 12 months after May 2025, shouldn't Intel 18A yield have reached at least 70%–80%, if not higher, regardless of how this 7% monthly improvement is measured?

i think it's measured relatively like x%x1.07%x1.07% so roughly yield at present x (rate of improvement ) raised to power number of months.

 

[MKWVentures]

i think it's measured relatively like x%x1.07%x1.07% so roughly yield at present x (rate of improvement ) raised to power number of months.

@hist78

Exactly: I can tell you that the yield in May 2026 was the yield (DPW) in May 2025 multiplied by 1.07^12.


After looking at all the data in retrospect, the initial yield, the yield learning rate and the current yield are not really that far off from the Plan of record. In May 2025, the lead product was ~8 months before product PRQ.

Now, that said..... the people who said 18A was mature in 2024 or manufacturing ready in March 2025 were crazy..... but it look decent now for a revolutionary process change 5 months after product PRQ. wafer Cost is the challenge.

 

[MKWVentures]

The NOT TSMC Market is growing. Remember, TSMC does not package other foundry dies so if the design isn't 100% TSMC packaging goes elsewhere, so this is not just a packaging capacity constraint.

Interesting points on this. Couple items:
1) TSMC does put HBM packages assembled by others onto CoWoS. They do not put logic die from other fabs on their packaging

2) One technical note for TSMC reasoning. It can be very difficult to control advanced packaging of logic die if you do not control the die manufacturing. Intel doing packaging of die for other people (where someone else did they wafer manufacturing could lead to some challenges on EMIB or Foveros type processing. Intel has seen issues with packaging Meteor lake and Panther lake (mixed Intel and TSMC die) and even arrow lake and lunar lake (all TSMC). those packages are not nearly as complex as DC product packaging

 

[hist78]

i think it's measured relatively like x%x1.07%x1.07% so roughly yield at present x (rate of improvement ) raised to power number of months.

@hist78

Exactly: I can tell you that the yield in May 2026 was the yield (DPW) in May 2025 multiplied by 1.07^12.


After looking at all the data in retrospect, the initial yield, the yield learning rate and the current yield are not really that far off from the Plan of record. In May 2025, the lead product was ~8 months before product PRQ.

Now, that said..... the people who said 18A was mature in 2024 or manufacturing ready in March 2025 were crazy..... but it look decent now for a revolutionary process change 5 months after product PRQ. wafer Cost is the challenge.

0.30 (initial yield) * 1.07^12 = 67.57%

0.35 (initial yield) * 1.07^12 = 78.83%

Can we assume that Intel's 18A yield has reached approximately 70% to 80% by now, given the reported 7% monthly improvements since May 2025?

Unless my assumption that the initial yield was around 30% to 35% is far from the actual situation?

 

[MKWVentures]

0.30 (initial yield) * 1.07^12 = 67.57%

0.35 (initial yield) * 1.07^12 = 78.83%

Can we assume that Intel's 18A yield has reached approximately 70% to 80% by now, given the reported 7% monthly improvements since May 2025?

Unless my assumption that the initial yield was around 30% to 35% is far from the actual situation?

I cant give exact numbers but, no, we cannot assume yield is 70% to 80% today. But your equation is correct. you are on the right track!!

 

[hist78]

Interesting points on this. Couple items:
1) TSMC does put HBM packages assembled by others onto CoWoS. They do not put logic die from other fabs on their packaging

2) One technical note for TSMC reasoning. It can be very difficult to control advanced packaging of logic die if you do not control the die manufacturing. Intel doing packaging of die for other people (where someone else did they wafer manufacturing could lead to some challenges on EMIB or Foveros type processing. Intel has seen issues with packaging Meteor lake and Panther lake (mixed Intel and TSMC die) and even arrow lake and lunar lake (all TSMC). those packages are not nearly as complex as DC product packaging

Do you know of any large volume Intel advanced packaging projects for external customers that have already been delivered?

You brought up a good point about the difficulty and complexity of Intel performing advanced packaging when most or all of the major components come from external manufacturers. It is challenging for Intel Foundry and its fabless customers to coordinate the technology and manufacturing processes when they have very limited control or no control at all over many of the components involved.

 

[hist78]

I cant give exact numbers but, no, we cannot assume yield is 70% to 80% today. But your equation is correct. you are on the right track!!

Wonderful! I can upgrade my Burger King lunch to celebrate this achievement.

In your opinion, is Intel at risk of being a little too late to align with the decision cycles of major fabless companies?

 

[MKWVentures]

Do you know of any large volume Intel advanced packaging projects for external customers that have already been delivered?

You brought up a good point about the difficulty and complexity of Intel performing advanced packaging when most or all of the major components come from external manufacturers. It is challenging for Intel Foundry and its fabless customers to coordinate the technology and manufacturing processes when they have very limited control or no control at all over many of the components involved.

the revenue would indicate that there are no large volume packaging projects for other companies in production as of Q1 2026. I am sure they are working details on packaging development projects and addressing the challenges.

If you told me to do a package as complex as Clearwater Forest using other peoples chiplets and base die, I would probably say "thats OK, I am going to pass". I am not sure what they are planning for external customers

 

[MKWVentures]

Wonderful! I can upgrade my Burger King lunch to celebrate this achievement.

In your opinion, is Intel at risk of being a little too late to align with the decision cycles of major fabless companies?

I think LBT did a great summary on this. First window was clearly missed for 18A.... everyone looked.... everyone passed. there is a lot of follow on opportunities for 18A for next 3-5 years

and LBT is trying to hit first window on 14A. I cannot imaging a company prioritizing Intel over TSMC until Intel delivers but you never know. @Daniel Nenni is the expert here (and as he always says there is the "NOT TSMC" market)