This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs. The emphasis of this course is …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Are FPGA booting challenges causing frustrating delays and leaving you uncertain about project timelines? Have you spent countless hours wrestling with boot image creation, only to encounter hardware dependencies or secure boot issues that stall progress? Eliminate the guesswork and …
Featured Speakers: Priyank Shukla, Director of Product Management, Synopsys Kent Lusted, Distinguished Architect, Synopsys Why You Should Attend: Understand Industry Readiness: Explore the challenges and opportunities in the race to 448G SerDes and …
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Designing DSP Applications with Versal AI Engines Workshop This workshop covers the AMD Versal AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of …
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Embark on a journey through semiconductor design, manufacturing, and business in this illuminating course. Explore IC design techniques, transistor evolution, and market dynamics. Delve into substrate types and industry economics, …
Gain a comprehensive understanding of the semiconductor industry and the integrated circuit (IC) manufacturing process. This course is designed for new personnel in the field or anyone seeking a well-rounded …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Join us to explore the functionality and configurability of the AMD Zynq UltraScale+ RFSoC. With …
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Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating …
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Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure. Gain hands-on experience with timing closure techniques and learn strategies to improve …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to …
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices. This …
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Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break …
Continue reading "Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques"
Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, …
