Abstract As AI workloads increasingly dominate numerous cloud and edge applications, building a scalable, efficient, and future-ready AI chips is no longer optional—it's essential. This webinar explores the latest AI …
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*WORK EMAIL IS REQUIRED* As data volumes surge across cloud, AI, automotive, and edge systems, efficient lossless compression has become essential for meeting performance, latency, and bandwidth constraints. This webinar …
This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs. The emphasis of this course is …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Are FPGA booting challenges causing frustrating delays and leaving you uncertain about project timelines? Have …
Designing DSP Applications with Versal AI Engines Workshop This workshop covers the AMD Versal AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Join us to explore the functionality and configurability of the AMD Zynq UltraScale+ RFSoC. With …
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Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating …
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Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for …
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover …
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Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break …
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Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, …
