Webinar: Why Choose PCIe 5.0 for Power, Performance, and Bandwidth at the Edge?

Online

Featured Speakers: Gustavo Pimentel, Principal Product Marketing Manager, Synopsys As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged as the optimal interconnect standard. Doubling the data rate of PCIe 4.0 while enabling lane reduction, PCIe 5.0 helps SoC designers achieve significant savings in …

Webinar: Enabling Tomorrow’s Workloads with 1.6Tbps Ethernet

Online

Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the need for robust pre-silicon verification has never been greater. Join this webinar to see how the Veloce™ hardware-assisted verification platform extends support for 1.6Tbps Ethernet …

Webinar: ML-Enhanced TCAD Calibration With 10x Reduction in Time to Results

Online

Date: Oct 15, 2025 | 5:00 PM PST Featured Speakers: Saurabh Suryavanshi, Product Manager, Synopsys Youngkwon Cho, Senior Staff Engineer, Synopsys Dipanjan Basu, Principal Engineer, Synopsys Calibration is an essential part of enabling TCAD products usages inside Semiconductor fab. Synopsys has been leading the development of ML-enhanced calibration that reduce the time to results by 10x while improve the …

Webinar: Pushing more power with CoolGaN™: design, layout and thermal management

Online

Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems. You will gain a deep understanding of gate drive circuit design, layout steps, and thermal management guidelines for GaN transistors and applications in high-switching frequency …

Achieving Timing Closure in FPGA Designs Workshop

Online

Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure. Gain hands-on experience with timing closure techniques and learn strategies to improve …

EU Chips Act 2.0 Webinar

Online

Europe's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative to strengthen the European semiconductor ecosystem. Building on the original Chips Act adopted in 2023, this updated framework aims to address emerging technologies such as …

Webinar: IP Design Considerations for Real-Time Edge AI Systems

Online

*Work Email Required* Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support real-time AI workloads at the edge. We’ll cover: • Memory and compute efficiency: Techniques for optimizing …

Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis

Online

The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL, and performing verification. An agile workflow requires being able to iterate through the …

Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System

Online

As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines machine learning, reinforcement learning, generative, and agentic AI across the …

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration

Online

Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications within a TSN framework. Join our hands-on demonstration to …

Webinar: 5 Expectations for the Memory Market in 2026

Online

October 29, 2025 - 11:00 AM EST    October 30, 2025 – 10:00 AM JST/KST Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026 AI workloads, HBM4 adoption, and 3D NAND scaling—what’s next for the memory industry in 2026. The memory semiconductor industry is entering a critical inflection point. Explosive AI workloads are pushing …

Webinar: 5 Expectations for the Sensor Market in 2026

Online

November 5, 2025 - 11:00 AM EST    November 6, 2025 – 10:00 AM JST/KST Discover the 5 Critical Sensor Market Trends Reshaping Semiconductors in 2026 From 8K smartphones to AI at the edge—explore the next generation of image sensor innovation. The image sensor industry is shifting from traditional pixel scaling to functionality-driven differentiation, unlocking new …