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As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will cover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We will cover the step-by-step design and verification of the Wake Word …
Featured Speakers: Gustavo Pimentel, Principal Product Marketing Manager, Synopsys As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged …
Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the …
Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems. …
Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, …
Europe's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative …
*Work Email Required* Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an …
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology …
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for …
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover …
Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break …
Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with …
