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About this event Join industry experts from NTT Innovative Devices, Lumentum, and Keysight to discuss their historic demonstration of 448g / lane signaling over PAM4 — a cross-continental collaboration that’s laying the foundation for the next generation of AI data centers and high-speed Ethernet. Who should attend this event? R&D engineers at network equipment manufacturers …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating complex workflows can feel overwhelming. The AMD Vitis™ Unified IDE simplifies the process by integrating Vitis IDE, Vitis Analyzer, and Vitis HLS into a single, …
Featured Speakers: Kiran Vittal, Synopsys Ayush Goyal, Synopsys As System-on-Chip (SoC) designs become increasingly complex, ensuring reliable Design-for-Test (DFT) connectivity at the RTL stage is more important than ever. This Synopsys webinar will demonstrate how static verification techniques, powered by TestMAX™ Advisor on the VC SpyGlass® platform, can help you address connectivity challenges efficiently and …
As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will cover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We will cover the step-by-step design and verification of the Wake Word …
Featured Speakers: Gustavo Pimentel, Principal Product Marketing Manager, Synopsys As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged as the optimal interconnect standard. Doubling the data rate of PCIe 4.0 while enabling lane reduction, PCIe 5.0 helps SoC designers achieve significant savings in …
Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the …
Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems. …
Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure. Gain hands-on experience with timing closure techniques and learn strategies to improve …
Europe's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative to strengthen the European semiconductor ecosystem. Building on the original Chips Act adopted in 2023, this updated framework aims to address emerging technologies such as …
*Work Email Required* Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support real-time AI workloads at the edge. We’ll cover: • Memory and compute efficiency: Techniques for optimizing …
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for …
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover …
Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break …
Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, …
