About DVCON DVCon Taiwan is the premier conference for design and verification engineers, researchers, and managers in Taiwan's semiconductor and EDA industries. Now in its third year, DVCon Taiwan 2025 continues its mission to bring together the local and international community to exchange ideas, explore the latest methodologies, and discuss emerging trends in design and …
Speaker: Hong-Cheang Quek, AE Director 10:00am~11:00am iPegasus Verification System for Virtuoso Studio 11:00am~11:15am Q&A Description: Today's complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence …
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