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About DVCON DVCon Taiwan is the premier conference for design and verification engineers, researchers, and managers in Taiwan's semiconductor and EDA industries. Now in its third year, DVCon Taiwan 2025 …
Speaker: Hong-Cheang Quek, AE Director 10:00am~11:00am iPegasus Verification System for Virtuoso Studio 11:00am~11:15am Q&A Description: Today's complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. …
Hyatt Regency Hotel, Santa Clara, CA
Santa Clara, CA, United States
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is …