Share your work, insights, and breakthroughs. The 2026 call for papers is open. SPIE Photonics West is the world’s largest optics and photonics technologies event. Present your research in biomedical optics, biophotonics, industrial lasers, optoelectronics, microfabrication, displays, quantum, and emerging vision technologies. Conferences and Courses: 17–22 January This is the place to be in January …
About this event Be the first to see brand new, Keysight-commissioned research on Cybersecurity Maturity Model Certification (CMMC) readiness across the U.S. Defense Industrial Base. In this live webinar, we’ll unveil findings from hundreds of security, IT, and compliance leaders and show where organizations really stand. Plus, attendees will be the first to get the full research paper, The Power of …
January 22-23, 2026, hosted by SEMI International, Silicon Valley, CA USA Note: HBS’26 is a hybrid event, with both in-person and virtual participation via WebEx. Download the Call for Presentations! Hybrid Bonding has emerged as the technology of choice in the semiconductor and heterogeneous integration industries for ultra-fine-pitch interconnection. With significant benefits for interconnect density and device …
About this event Stay connected with the latest optical design product innovations across CODE V, LightTools, RSoft, ImSym, and our optical scattering measurement solutions. Get tips and tricks on design best practices from our experts, and network with industry peers and the Keysight Optical Design Engineering team. The user conference is held in parallel with …
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The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday, January 27, 2026, at the NIST National Cybersecurity Center of Excellence (NCCoE) conference facility, in Rockville, Maryland. This in-person, one-day event builds on the momentum from the April 2025 workshop on Trust and Provenance in the Semiconductor Supply Chain, …
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Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process. …
In this webinar, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks. We will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily …
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Intro The Compact-Q DEER Spectrometer is designed to support researchers in academia and industry to efficiently characterize quantum materials, develop devices for quantum sensing, advance and validate algorithms to control qubits, and other applications in spin-based quantum technologies. The Compact-Q DEER system features a modern microwave architecture, high-resolution AWG, and digital signal processing schemes enabling …
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Date: Feburary 11-13, 2026 Hours February 11, 2026 | 10:00-17:00 (Last entry 16:30) February 12, 2026 | 10:00-17:00 (Last entry 16:30) February 13, 2026 | 10:00-16:00 (Last entry 15:30) Venue COEX (Hall A, B, C, D, E, Grand Ballroom, Platz and ASEM Ballroom) Westin Seoul Parnas Grand InterContinental Seoul Parnas Scale 550 Exhibitors, 2411 booths …
About ISSCC The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts. What’s New Download the ISSCC 2026 …
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All the Solutions for Developing Chiplets 2025 Keynote Addresses from Industry Leaders: Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne 2025’s Main Topics Included: AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries signup to be a 2026 SPONSOR / Exhibitor REGISTER HERE
Formatting Advanced Packaging for the Next Generation The evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package …
