Events

Traditional RTL low power design techniques such as sequential clock gating are widely deployed across the industry. Yet, even after multiple RTL revisions, residual power inefficiencies often remain undetected until silicon, resulting in missed optimization opportunities. This seminar presents a refined approach to conventional methodologies: a reporting and opportunity identification layer that sits atop clock …

Continue reading "Webinar: From RTL to Silicon: Qualcomm Closes the Power Gap with Module-Level Insights"