The National Institute of Standards and Technology (NIST) will host the Semiconductor Traceability and Provenance Workshop on Tuesday, October 21, 2025, at its campus in Gaithersburg, Maryland. This in-person, one-day …
Continue reading "Semiconductor Traceability and Provenance Workshop"
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive, data …
Event Summary The year 2025 is both a turning point for integrated photonics as a key enabler for AI, physical and infrastructure interconnect, and the International Year of Quantum (IYQ). …
Continue reading "CadenceCONNECT: Photonics and Quantum Technologies"
Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems. …
Continue reading "Webinar: Pushing more power with CoolGaN™: design, layout and thermal management"
Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, …
Continue reading "Achieving Timing Closure in FPGA Designs Workshop"
October 22, 2025 - 11:00 AM EST October 23, 2025 – 10:00 AM JST/KST Discover the 5 Critical Power Market Trends Reshaping Semiconductors in 2026 Wide-bandgap disruption, PMIC innovation, and …
Continue reading "Webinar: 5 Expectations for the Power Market in 2026"
Europe's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative …
*Work Email Required* Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support real-time AI workloads at the edge. We’ll cover: • Memory and compute efficiency: Techniques for optimizing …
Continue reading "Webinar: IP Design Considerations for Real-Time Edge AI Systems"
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn't just an event; it's a dynamic hub where the brightest minds converge to ignite the next wave of innovation. As the AI …
Continue reading "2025 TSMC Open Innovation Platform Ecosystem Forum – Tokyo"
The 2025 International Conference on Computer-Aided Design Call For Papers Jointly sponsored by IEEE and ACM, IEEE ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas. IEEE ICCAD covers the full range of CAD topics – from device and circuit …
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL, and performing verification. An agile workflow requires being able to iterate through the …
CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world to share the latest design and verification practices based on Cadence’s Jasper formal verification technologies and methodologies. The Jasper User Group Conference is the premier …
