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In this webinar, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks. We will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily …
As hardware designs grow more complex, architectural exploration is increasingly critical to delivering differentiated silicon. Teams frequently develop promising architectures only to discover late in the cycle that physical implementation is too costly or fails to meet key specifications. This challenge intensifies as designers integrate new accelerators — video, audio, ML, or custom datapaths — …
Date: Feb 04, 2026 | 9:00 AM PST Featured Speakers: Dr. Yervant Zorian , Chief Architect and Fellow at Synopsys, President of Synopsys Armenia Dr. Sandeep K Goel, Senior Director, TSMC Our upcoming Synopsys webinar features an exciting real-world case study showcasing Synopsys IP and EDA tools with UCIe-based chiplets on advanced TSMC silicon and packaging technologies. See firsthand the …
Date: Feb 05, 2026 | 9:00 AM PST Featured Speakers: Varun Agrawal, Product Manager, Synopsys Jon Ames, Product Manager, Synopsys Discover how UALink enables open, scalable, secure interconnects for AI workloads—and how Synopsys IP and VIP accelerate adoption. Why You Should Attend: Learn about UALink advantages over proprietary interconnects for AI scalability and security. Explore open ecosystem benefits: multi-vendor interoperability …
Join us for Demo Day – Signal Generators and discover how to accelerate and optimize RF testing with the capabilities offered by these instruments in our test bench. Learn how to perform power amplifier matching correction with a signal generator's integrated reflectometer in minutes… not hours. No additional test equipment required. We will also demonstrate how the …
Intro The Compact-Q DEER Spectrometer is designed to support researchers in academia and industry to efficiently characterize quantum materials, develop devices for quantum sensing, advance and validate algorithms to control qubits, and other applications in spin-based quantum technologies. The Compact-Q DEER system features a modern microwave architecture, high-resolution AWG, and digital signal processing schemes enabling …
San Francisco Marriott Marquis
San Francisco Marriott Marquis, 780 Mission Street, San Francisco, CA, United States
About ISSCC The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts. What’s New Download the ISSCC 2026 …
Santa Clara Convention Center
Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA, United States
All the Solutions for Developing Chiplets 2025 Keynote Addresses from Industry Leaders: Alphawave Semi, Arm, Cadence Design Systems, Keysight, Open Compute Project, Synopsys, Teradyne 2025’s Main Topics Included: AI/ML Acceleration, Open Chiplet Economy, Advanced Packaging Methods, Die-to-die Interfaces, Working with Foundries signup to be a 2026 SPONSOR / Exhibitor REGISTER HERE
Aerospace, defense, and other mission-critical technologies face rapidly evolving hardware threats. A hobbyist can add a single board computer to a consumer device. A nation-state can scale an exploit across critical infrastructure. The attack surface widens fast, and the security implications are real. Adversaries are continuously developing techniques that can compromise mission-critical components, sometimes before …
Hyatt Regency San Francisco Airport
1333 Bayshore Highway, Burlingame, CA, United States
Formatting Advanced Packaging for the Next Generation The evolution of Advanced Package Technology is experiencing substantial changes as system designs directly drive package performance requirements—an unprecedented development in the industry. Historically, architects constructed circuits within packaging constraints to prevent undesirable outcomes. Nevertheless, increasing transistor expenses and the demand for improved power efficiency necessitate advancing package …
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today's application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately, the SAF model is a poor model for defects. Other models and strategies are required to catch …
