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Will my High-Speed Serial Link Work?

Will my High-Speed Serial Link Work?
by Daniel Payne on 04-30-2024 at 10:00 am

traditional flow min

PCB designers can perform pre-route simulations, follow layout and routing rules, hope for the best from their prototype fab, and yet design errors cause respins which delays the project schedule. Just because post-route analysis is time consuming doesn’t mean that it should be avoided. Serial links are found in many PCB designs,… Read More


Enabling Imagination: Siemens’ Integrated Approach to System Design

Enabling Imagination: Siemens’ Integrated Approach to System Design
by Kalar Rajendiran on 04-30-2024 at 6:00 am

Siemens EDA Important to Siemens

In today’s rapidly advancing technological landscape, semiconductors are at the heart of innovation across diverse industries such as automotive, healthcare, telecommunications, and consumer electronics. As a leader in technology and engineering, Siemens plays a pivotal role in empowering the next generation … Read More


Design Stage Verification Gives a Boost for IP Designers

Design Stage Verification Gives a Boost for IP Designers
by Mike Gianfagna on 04-25-2024 at 6:00 am

Design Stage Verification Gives a Boost for IP Designers

The concept of shift left is getting to be quite well-known. The strategy involves integrating various checks typically performed later in the design process into earlier stages. The main benefit is to catch and correct defects or errors at an earlier stage when it’s easier and faster to address. For complex SoC design, … Read More


Checking and Fixing Antenna Effects in IC Layouts

Checking and Fixing Antenna Effects in IC Layouts
by Daniel Payne on 03-14-2024 at 10:00 am

Planar CMOS cross-section – antenna DRC

IC layouts go through extensive design rule checking to ensure correctness, before being accepted for fabrication at a foundry or IDM. There’s something called the antenna effect that happens during chip manufacturing where plasma-induced damage (PID) can lower the reliability of MOSFET devices. Layout designers run Design… Read More


Siemens Promotes Digital Threads for Electronic Systems Design

Siemens Promotes Digital Threads for Electronic Systems Design
by Bernard Murphy on 03-06-2024 at 6:00 am

Digital threads min

Many years ago, I remember discussions around islands of automation/silos. Within the scope of any given silo there is plenty of automation to handle tasks relevant to that phase. But managing the full lifecycle from concept through manufacturing to field support must cross between silos, and those transitions are not as clean… Read More


Designing for Security for Fully Autonomous Vehicles

Designing for Security for Fully Autonomous Vehicles
by Kalar Rajendiran on 03-05-2024 at 10:00 am

OSI Seven layer model for securing network communication

With the advent of IoT devices, vehicles have become increasingly interconnected, offering enhanced automation, connectivity, electrification, and shared mobility. However, this progress also brings forth unprecedented challenges, particularly in ensuring the safety and security of automotive electronics. The complexity… Read More


INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with advanced analog and mixed-signal EDA technology

INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with advanced analog and mixed-signal EDA technology
by Daniel Nenni on 03-05-2024 at 6:00 am

siemens symphony interchip large

Customer case studies have always been my favorite source of information. Press releases are a great start but there is always more to the story. Fortunately, I had the opportunity to speak with Sumit Vishwakarma, principal product manager at Siemens EDA about their recent press release with Interchip. I was an advisor to Berkeley… Read More


A Game-Changer for IP Designers: Design Stage Verification

A Game-Changer for IP Designers: Design Stage Verification
by Kalar Rajendiran on 03-04-2024 at 10:00 am

Calibre Shift Left Solutions Enable Reducing TTM

In today’s rapidly evolving semiconductor industry, the design and integration of intellectual property (IP) play a pivotal role in achieving competitive advantage and market success. Whether sourced from commercial IP providers or developed in-house, ensuring that IP designs are compliant with signoff requirements… Read More


Soft checks are needed during Electrical Rule Checking of IC layouts

Soft checks are needed during Electrical Rule Checking of IC layouts
by Daniel Payne on 02-28-2024 at 10:00 am

Metal1 Via Metal2 s

IC designs have physical verification applications like Layout Versus Schematic (LVS) at the transistor-level to ensure that layout and schematics are equivalent, in addition there’s an Electrical Rules Check (ERC) for connections to well regions called a soft check. The  connections to all the devices needs to have the most… Read More


New Emulation, Enterprise Prototyping and FPGA-based Prototyping Launched

New Emulation, Enterprise Prototyping and FPGA-based Prototyping Launched
by Daniel Payne on 02-26-2024 at 10:00 am

Veloce Strato CS min

General purpose CPUs have run most EDA tools quite well for many years now, but if you really want to accelerate something like simulation then you start to look at using specializedhardware accelerators. . Emulators came onto the scene around 1986 and the processing power has greatly increased over the years, mostly in response… Read More