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An update here: https://frederickchen.substack.com/p/stochastic-pupil-fill-in-euv-lithography, particularly relevant to Stochastic Effect of Large Pupil Fill.
Are you passionate about RISCV and Semiconductor industry? We need you! As a Junior NoC Design Engineer, you will collaborate in building Network-on-Chip solutions for our semiconductor portfolio. You will work with the NoC Design Team and work closely with other teams’ highly skilled engineers to create efficient, high-performance and extremely configurable on-chip communication networks that are essential for modern designs.
What we offer? Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required)
Requirements
Master or Doing Master
English C1
Industrial experience +2 years
Knowledge of scripting languages (Python, Perl, Bash, TCL)
Experience of RTL Linting
Familiarity with simulation tools
Experience with Timing and Timings Constraints
Knowledge of revision control methodology and tools ( git, svn)
Experience with basic block level testing
Strong problem-solving skills and attention to detail
An update here: https://frederickchen.substack.com/p/stochastic-pupil-fill-in-euv-lithography, particularly relevant to Stochastic Effect of Large Pupil Fill.
If you believe in Hobbits you can believe in Rapidus