Verification Engineer – II

Logic verification, UVM, system level verification, automation/scripting, coverage analysis, functional coverage, basic perl, synthesis, CDC/RDC analysis.

Experience: 5 + yrs

Behaviors:

• English fluent

• Good communication at designer level and management level,

• Positive person

• High customer orientation

• Curious to learn and adapt

• managing ambiguity and design conflicts

• Fast learning

• Flexible and adaptive

• own BU challenges as his / her and work with BU design teams for resolution