Lead Design Engineer

Principal Logic Design Engineer

As a member of the Logic Design Team for Xtensa processors you will be responsible for the micro-architecture development and specification of microprocessor cores, multiprocessor sub-systems and their peripherals. You will design and implement the micro-architecture in Verilog or SystemVerilog RTL, simulate and debug its functions and run synthesis, place & route and other EDA scripts to meet timing, area and power goals. You will also assist with developing testplans, writing functional diagnostics, debugging failures and analyzing coverage information. You will work closely with the Design Verification and EDA teams.

The Position Requirements are:

BS (or higher) in EE /Computer Engg. with 3-6 years of relevant experience.
Excellent logic design skills as demonstrated by successful ASIC or SoC implementations.
Knowledge of computer architecture and pipelined designs is required. Experience with processor instruction fetch micro-architecture development a huge plus.
Excellent knowledge of Verilog/SystemVerilog and popular EDA simulation & implementation tools
Good experience in scripting languages like Perl, Unix shell or similar languages.
Some experience with state-of-the-art verification methodologies (ex RTL assertions, coverage, etc) and assembly language programming required.
Excellent written and oral communication skills necessary.