Single HW/SW Bill of Material (BoM) Benefits System Development

Single HW/SW Bill of Material (BoM) Benefits System Development
by Daniel Payne on 02-23-2021 at 10:00 am

Perforce - IP

Most large electronics companies take a divide and conquer approach to projects, with clear division lines set between HW and SW engineers, so quite often the separate teams have distinct methodologies and ways to design, document, communicate and save a BoM. This division can lead to errors in the system development process,… Read More


Third Generation of IP Lifecycle Management Launched

Third Generation of IP Lifecycle Management Launched
by Daniel Payne on 11-17-2020 at 10:00 am

Methodics and Perforce

Back in July I first read the news that Perforce had acquired Methodics, and wasn’t too surprised, because many of the EDA vendors that we blog about do get acquired or merge with similar sized companies in order to be part of a bigger offering. When Methodics announced a webinar introducing IPLM 3.0 (IP Lifecycle Management),… Read More


What’s At the Center of Your SoC Design Process?

What’s At the Center of Your SoC Design Process?
by Daniel Payne on 06-15-2020 at 10:00 am

IP SoC min

I love starting a new project from scratch, because there’s that optimistic feeling of having no constraints and being able to creatively express myself and get the job done right this time. For SoC designs today there are teams of engineers and maybe a program manager plus a marketing person that define the features, budget… Read More


Project-Centric Design Process, or IP-centric

Project-Centric Design Process, or IP-centric
by Daniel Payne on 04-14-2020 at 10:00 am

projects

How do most IC design teams organize their work during the design process?

Most design teams would say that they organize their work into a project-centric view, and that at the beginning of the process use a tool for requirements management, maybe a bug tracker, or some design management tool. On the four IC designs that I worked … Read More


Avoiding Fines for Semiconductor IP Leakage

Avoiding Fines for Semiconductor IP Leakage
by Daniel Payne on 12-24-2019 at 10:00 am

Percipient IPLM

In my semiconductor and EDA travels I’ve enjoyed visiting engineers across the USA, Canada, Europe, Japan, Taiwan and South Korea. I’ll never forget on one trip to South Korea where I was visiting a semiconductor company and upon reaching the lobby a security officer asked me to take out my laptop computer, because he wanted me to… Read More


Webinar Recap: IP Security Threats in your SoC

Webinar Recap: IP Security Threats in your SoC
by Daniel Payne on 11-28-2019 at 10:00 am

Methodics Security SoC

Three years ago my youngest son purchased a $17 smart watch on eBay, but then my oldest son read an article warning about how that watch would sync with your phone, then send all of your contact info to an address in China. My youngest son then wisely turned the watch off, and never used it again. Hackers have been able to spoof and hide Read More


IP Lifecycle Management and Permissions

IP Lifecycle Management and Permissions
by Daniel Payne on 07-29-2019 at 10:00 am

Percipient IPLM

My first professional experience with computers and file permissions was at Intel in the late 1970s, where we used big iron IBM mainframes located far away in another state, and each user could edit their own files along with browse shared files from co-workers in the same department. I saw this same file permission concept when … Read More


Webinar: ISO 26262 Compliance

Webinar: ISO 26262 Compliance
by Daniel Payne on 05-02-2019 at 12:00 pm

To me the major idea of ISO 26262 compliance is ensuring that requirements can be traced throughout the entire design and verification process, including the use of IP blocks. The first market application that comes to mind with ISO 26262 is automotive, with its emphasis on safety because human lives are at stake. Since necessity… Read More


Cloud-based Functional Verification

Cloud-based Functional Verification
by Daniel Payne on 04-08-2019 at 12:00 pm

The big three EDA vendors are constantly putting more of their tools in the cloud in order to speed up the design and verification process for chip designers, but how do engineering teams approach using the cloud for functional verification tests and regressions? At the recent Cadence user group meeting (CDNLive) there was a presentation… Read More


Traceability and Design Verification Synergy

Traceability and Design Verification Synergy
by Daniel Payne on 03-14-2019 at 12:00 pm

The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We’ve all heard the maxim, “Work smarter, not harder.” A white paper just came out from Methodics on a smarter approach, Traceability… Read More