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A Fill Solution for 20nm at TSMCby glforte on 03-17-2014 at 5:12 pmCategories: EDA, Siemens EDA
By Jeff Wilson, Mentor Graphics
We’ve talked about the new requirements for Fill in IC design for advanced nodes in previous blogs on this site. This time I’d like describe the fill solution that Mentor and TSMC have jointly developed to meet the requirements of fill for TSMC’s 20nm (N20) manufacturing process.
The traditional… Read More
