The Sky’s the Limit: SiFive’s BigSky Brings RISC-V to the Datacenter

The Sky’s the Limit: SiFive’s BigSky Brings RISC-V to the Datacenter
by Daniel Nenni on 08-24-2026 at 6:00 am

The Sky’s the Limit SiFive’s BigSky Brings RISC V to the Datacenter

SiFive is bringing RISC-V closer to mainstream datacenter deployment with the BigSky SF-2U870, an enterprise-grade development server designed for hyperscalers, semiconductor companies, software vendors, and ecosystem partners. Announced in Santa Clara on August 24, 2026, alongside Hot Chips, the rackable 2U platform… Read More


CEO Interview with Sumeet Kumar of Innatera

CEO Interview with Sumeet Kumar of Innatera
by Daniel Nenni on 08-23-2026 at 8:00 am

SK Headshot 2 (1)

Dr. Sumeet Kumar is CEO of Innatera, the pioneering Dutch neuromorphic processor company. Dr. Kumar was previously with Intel and Indrion Technologies, and has spent his career in microprocessor development. He co-founded Innatera in 2018 as a spin off from the Delft University of Technology.

Tell us about your company?

When… Read More


The First Real RISC-V AI Laptop

The First Real RISC-V AI Laptop
by Jonah McLeod on 03-17-2026 at 6:00 am

DC ROMA

At a workshop in Boston on February 27, something subtle but important happened. Developers sat down in front of a RISC-V laptop, installed Fedora, and ran a local large language model. No simulation. No dev board tethered to a monitor. A laptop.

For more than a decade, RISC-V advocates have promised that the open instruction set… Read More


Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security

Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security
by Kalar Rajendiran on 05-13-2025 at 6:00 am

Information Flow Analysis Cycuity's Unique Approach

As RISC-V adoption accelerates across the semiconductor industry, so do the concerns about hardware security vulnerabilities that arise from its open and highly customizable nature. From hardware to firmware and operating systems, every layer of a system-on-chip (SoC) design must be scrutinized for security risks. Unlike… Read More


TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor
by Wenbo Yin on 09-10-2024 at 10:00 am

MX100

The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications has driven an unprecedented demand for specialized compute acceleration not met by conventional von Neumann architectures. Among the competing alternatives, one showing the greatest promise is analog in-memory computing… Read More