Webinar: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance

Webinar: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performance
by Admin on 05-23-2023 at 2:26 pm

Date: Wednesday, June 7, 2023

Time: 11:00 am PDT | 2:00 pm ET | 8:00 pm CEST

Xcelium mixed-signal simulation enables teams to achieve digital simulation speeds of analog models and opens mixed-signal designs to advanced verification techniques typically applied within standard verification flows.  Built on a SystemVerilog… Read More


WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING

WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING
by Admin on 06-16-2020 at 6:26 am

Webinar Details

Creating Assertions for SV Real-Number Modeling
Date: Wednesday, June 17, 2020
Time: 09:00 EDT / 14:00 BST / 15:00 CEST / 18:30 IST

Questions about this event?

Send email to: eur_training@cadence.com

Device assertions and checks have been used in analog simulation for years. These checks, however, are more

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