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An update on the Design Productivity Gapby Tom Dillinger on 08-03-2018 at 12:00 pmCategories: Cadence, EDA
Over a decade ago, a group of semiconductor industry experts published a landmark paper as part of the periodic updates to the International Technology Roadmap for Semiconductors, or ITRS for short (link). The ITRS identified a critical design productivity gap. The circuit capacity afforded by the Moore’s Law pace of technology… Read More