WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING

WEBINAR: CREATING ASSERTIONS FOR SV REAL-NUMBER MODELING
by Admin on 06-17-2020 at 12:00 am

Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, impedance, and timing rather than functionality.

The SystemVerilog language supports assertions (SVA) for functional verification. By extending the MS

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High Speed SerDes Design and Simulation Webinar Replay from Mentor

High Speed SerDes Design and Simulation Webinar Replay from Mentor
by Tom Simon on 05-14-2020 at 10:00 am

Mentor SerDes Simulation

Over the years SerDes (serializer/deserializer) based connections have proliferated into just about every connection within and among computing systems. Years ago, parallel interfaces were the most common method of moving data, but issues of signal integrity, synchronization and power simply became too much for the required… Read More