Over the years SerDes (serializer/deserializer) based connections have proliferated into just about every connection within and among computing systems. Years ago, parallel interfaces were the most common method of moving data, but issues of signal integrity, synchronization and power simply became too much for the required… Read More
Device assertions and checks have been used in analog simulation for years. These checks, however, are more focused on device characteristics such as voltage, current, impedance, and timing rather than functionality.
The SystemVerilog language supports assertions (SVA) for functional verification. By extending the MS