Verifying circuits on advanced process nodes has always been difficult, and it’s no easier with today’s nanometer CMOS processes. There’s a great paradox in nanometer circuit design and verification. Designers achieve their greatest differentiation when they implement analog, mixed-signal, RF and custom … Read More
The 48[SUP]th[/SUP] Design Automation Conference (DAC) is now upon us. DAC is billed as “the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions” for which I would have to agree with 100%.
The first DAC I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow … Read More
For those of you who follow the market and play EDA stocks this will be a shocker! Jim Cramer, former Hedge Fund Manager, co-founder of TheStreet.com, and host of the CNBC’s Mad Money did a piece last week on Cadence. Apparently he did NOT read my piece on EDA being DEAD:
Cramer’s Wednesday “Tech Spec” pickswas Cadence Design Systems… Read More
