Tag: ir2.0

CadenceCONNECT: IR2.0 – Building a New Paradigm for Power Integrity Design and Analysis

CadenceCONNECT: IR2.0 – Building a New Paradigm for Power Integrity Design and Analysis
by Admin on 10-04-2023 at 5:04 am

Date: November 2, 2023

Time: 10:00am – 5:00pm

Location: Cadence Headquarters, San Jose, CA | Building 10 – Auditorium

Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding

… Read More