Custom Layout Productivity Gets a Boost

Custom Layout Productivity Gets a Boost
by Tom Dillinger on 04-11-2016 at 7:00 am

In the 1970’s, when Moore’s Law was still in its infancy, Bill Lattin from Intel published a landmark paper [1]. In it he identified the need for new design tools and methods to improve layout productivity, which he defined as the drawn and verified number of transistors per day per layout designer. He said existing … Read More


IC Implementation Tool Gets a Rewrite, Now 10X Faster

IC Implementation Tool Gets a Rewrite, Now 10X Faster
by Daniel Payne on 03-24-2014 at 10:05 am

EDA start-up companies often have the advantage over established vendors by being able to start from scratch, instead of having to maintain some legacy code that no longer is competitive. But what happens when the established vendor decides to rewrite their IC implementation tools from scratch? In this case it’s good news,… Read More